Detecting Polysilicon Residue in LOCOS Etching
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Solution Overview
Problem
The miniaturization of transistor gate line widths in semiconductor device processing is hindered by the micro-loading effect and uneven topography, leading to difficulties in etching and clearing conductive materials, particularly in narrow regions, which existing test structures like the serpentine/comb structure are unable to reliably detect.
Innovation Solution
A test structure comprising a PMOS transistor and a one-time programmable EPROM with probe contacts is used to apply specific voltages and measure currents, allowing for the detection of residual conductive material and gross processing errors, distinguishing between functional and non-functional devices and identifying polysilicon residue on the source and drain sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If photolithography is used to form narrower control gates for miniaturization, then device size is reduced, but etching reliability deteriorates due to micro-loading effect and uneven topography
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the actual gate etching process. This mandrel serves as a template that defines the narrow gate regions, allowing the etch to proceed uniformly without suffering from micro-loading effects. The mandrel is removed after defining the pattern, leaving clean narrow gates without residue issues.
Solution Approach 2:
The mandrel acts as an intermediary structure that mediates between the photolithography pattern and the final gate structure. It provides a physical framework that ensures uniform etching across both narrow and wide regions, preventing the micro-loading effect from causing incomplete removal or overetching.
2Measurement precision
If conventional serpentine/comb test structures are used to detect processing errors, then large feature detection is enabled, but small polysilicon residue detection capability is insufficient
Solution Approach 1:
The patent applies local quality by creating test structures with specifically designed narrow regions that match the critical dimensions of actual device gates. These localized test features have the same width and spacing as the production gates, enabling detection of polysilicon residues in the critical narrow regions where conventional large-featured test structures fail.
Solution Approach 2:
The patent changes the dimensional parameters of the test structures, specifically reducing the width and spacing of test features to match the miniaturized gate dimensions. This parameter change enables the test structure to detect residues at the same scale as actual devices, overcoming the limitation of conventional large-featured test structures.
Data Source
AI summary
A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.