LOFIC Pixel Cell Reset Circuit for Faster Settling and Readout
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Solution Overview
Problem
As the capacitance of lateral overflow integration capacitors (LOFICs) in pixel cells increases, so does the time required for charging and resetting, leading to longer row LOFIC charge and reset times, which can result in image artifacts like banding, especially in larger pixel arrays where the total capacitance load on global row drivers increases, making it challenging to maintain frame rates without violating timing specifications.
Innovation Solution
Incorporating reset transistors between LOFICs and a supply voltage, allowing for local reset and auto-zeroing of LOFICs, reducing the need for global row drivers and enabling faster precharge and readout operations by locally pulling the LOFIC ends toward the supply voltage, thus reducing reset and settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If LOFIC capacitance is increased to improve dynamic range, then full well capacity is improved, but charge and reset times increase causing image artifacts and decreased frame rates
Solution Approach 1:
The patent divides the LOFIC reset operation into two independent phases: a fast auto-zero phase that equalizes voltage between LOFIC nodes, and a subsequent charge phase. This segmentation allows the critical auto-zeroing to complete quickly regardless of LOFIC capacitance size, while the charge phase can proceed at optimal speed, thereby resolving the contradiction between large capacitance and fast reset time
Solution Approach 2:
The patent performs auto-zeroing of the LOFIC before the main charge operation. By preliminarily equalizing the voltage potential across the LOFIC nodes through the auto-zero transistor, the system prepares the capacitor for rapid charging without being constrained by its full capacitance value during the critical reset phase, thus enabling faster overall reset times even for large capacitance LOFICs
2Quantity of substance
If LOFIC capacitance is increased to improve dynamic range, then full well capacity is improved, but frame rate decreases due to longer charging and resetting times
Solution Approach 1:
The patent segments the LOFIC operation timeline into distinct phases: auto-zeroing phase followed by charge phase. This allows the system to perform the time-critical auto-zeroing operation quickly using the auto-zero transistor, then proceed with capacitor charging at optimal rates, thereby maintaining high frame rates even with large LOFIC capacitance values that provide improved dynamic range
Solution Approach 2:
The patent changes the operational parameters of the LOFIC by introducing controlled voltage transitions through the auto-zero transistor. By dynamically adjusting the voltage potential across the LOFIC nodes during auto-zeroing, the system optimizes the charging characteristics of large capacitance LOFICs, enabling faster charge and reset cycles that support higher frame rates while maintaining large capacitance for improved dynamic range
3Quantity of substance
If LOFIC capacitance is increased to improve dynamic range, then full well capacity is improved, but image artifacts increase due to insufficient reset time
Solution Approach 1:
The patent performs preliminary auto-zeroing of the LOFIC nodes before the main charge operation begins. By equalizing the voltage potential across the LOFIC capacitance in advance through the auto-zero transistor, the system eliminates residual charge imbalances that would otherwise cause image artifacts, thereby ensuring clean, artifact-free images even when using large capacitance LOFICs for improved dynamic range
Solution Approach 2:
The patent implements a rapid auto-zeroing phase that quickly equalizes voltage across the LOFIC nodes before proceeding to the main charge operation. This rushed-through preliminary step ensures that any residual charge imbalances are eliminated in minimal time, preventing image artifacts while allowing the subsequent charge phase to utilize the full capacitance value for improved dynamic range
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the use of higher capacitance LOFICs and larger pixel arrays without increasing precharge and reset timing margins, enabling faster frame rates and reducing the risk of image artifacts like banding.
Implementation Method 1
The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light
Data Source
AI summary
Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.