Log Block Mapping Tables for NAND Flash Memory Management
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Solution Overview
Problem
Non-volatile memory devices, particularly NAND flash memory, face inefficiencies in data read, write, and erase operations due to high read and write times, and the need for simultaneous erasure of multiple memory cells, which complicates data management and address translation.
Innovation Solution
A memory device architecture that includes data blocks, log blocks, and metablocks for efficient data management, utilizing spare areas for mapping tables to store updated data values and mapping information, allowing for efficient page-level updates and reads by calculating logical and physical block addresses, and managing clean pages and log blocks to optimize storage and retrieval processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If mapping tables are stored in dedicated memory areas, then address translation functionality is ensured, but storage space is consumed
Solution Approach 1:
The patent merges the mapping table storage with the spare area of log blocks. Instead of allocating separate dedicated memory for mapping tables, the invention combines address translation data with existing log block structures, allowing mapping information to be stored alongside updated data values in the same memory space.
Solution Approach 2:
The spare area of log blocks is given multiple functions: it originally served for error correction codes and metadata, and now also stores mapping tables. This multi-functional use of the spare area eliminates the need for separate mapping table storage while maintaining address translation capabilities.
2Speed
If data is updated in place, then write speed is improved, but address management complexity increases due to logical-physical address conversion
Solution Approach 1:
The patent introduces a log block as an intermediary structure between the data block and the host. The log block contains a mapping table that translates logical addresses to physical addresses, mediating the address conversion process and enabling efficient in-place updates while managing address translation complexity centrally.
Solution Approach 2:
The log block structure is designed to be self-sufficient with embedded mapping tables that automatically handle address translation. When data is updated, the system uses the mapping information already present in the log block's spare area to perform address conversion without requiring external address management mechanisms.
3Loss of time
If erase operations are performed on entire blocks, then erase time is reduced, but data loss in non-target areas occurs
Solution Approach 1:
The patent segments the memory structure into data blocks and log blocks with distinct functions. The log block contains mapping tables that identify which specific pages within a block contain updated data. This segmentation allows selective erasure operations that target only necessary data while preserving other information, avoiding the need to erase entire blocks.
Solution Approach 2:
The mapping tables in the log block are prepared in advance to identify valid data locations before erase operations. This preliminary mapping information allows the system to determine which specific pages need erasure, enabling targeted erase operations that avoid unnecessary data loss while maintaining efficient erase timing.
Data Source
AI summary
A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data.