Log-Domain Polynomial Kernel Generator for Full-Duplex Self-Interference
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Solution Overview
Problem
Nonlinear systems in full-duplex radio communication face challenges such as out-of-band emissions and in-band distortion due to dynamic nonlinearity, leading to low energy efficiency and performance degradation, particularly in self-interference cancellation where high computational complexity and power costs hinder accurate hardware realization.
Innovation Solution
A polynomial kernel generator component that operates without multipliers, using logarithmic computations and piecewise polynomial approximations to cancel nonlinear transmitter interference, achieving efficient hardware realization with a K+1 cycle delay and supporting configurable multi-kernel architectures for energy-efficient self-interference cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonlinear pre- or post-distortion schemes are used to mitigate out-of-band emissions and in-band distortion, then performance is improved, but energy efficiency deteriorates due to high computational complexity
Solution Approach 1:
The patent transforms the computational domain by converting polynomial computations from the linear domain to the log domain. This parameter transformation changes the mathematical operations from multiplications to additions, significantly reducing computational complexity and energy consumption while maintaining the same nonlinear modeling capability for distortion mitigation
Solution Approach 2:
The patent replaces complex multiplication operations with simpler addition operations in the log domain. This substitution of computational mechanisms reduces the hardware complexity and energy requirements while achieving the same polynomial kernel generation function needed for nonlinear distortion compensation
2Measurement precision
If polynomial kernel generation with multipliers is used for accurate nonlinear modeling, then modeling precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces multiplier components with adder components by performing polynomial computations in the log domain. This substitution maintains modeling precision because the log-domain polynomial kernels are mathematically equivalent to linear-domain kernels, while dramatically reducing hardware complexity by eliminating expensive multiplier circuits
Solution Approach 2:
The patent introduces the logarithmic domain as an intermediary computational space. By transforming inputs through logarithms, performing polynomial operations in this intermediate domain, and then transforming back, the system achieves accurate nonlinear modeling without requiring complex multiplier hardware in the original domain
3Manufacturing precision
If high-degree polynomial approximations are used to accurately model nonlinear behavior, then manufacturing precision is improved, but loss of time increases due to longer computation cycles
Solution Approach 1:
The patent changes the computational parameter from linear-domain polynomial operations to log-domain polynomial operations. This parameter change allows high-degree polynomial approximations to be computed more efficiently because addition operations in the log domain are faster and can be parallelized more effectively than multiplication operations in the linear domain, reducing computation time while maintaining high modeling accuracy
Data Source
AI summary
A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.


