Logarithmic Addition-Accumulator Circuitry for Low-Overhead Inferencing
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Solution Overview
Problem
Current technologies face inefficiencies in processing image data using floating point formats, particularly in inferencing operations, as they require extensive conversion between formats, leading to increased computational complexity and power consumption.
Innovation Solution
The implementation of logarithmic addition-accumulator circuitry that converts input data and filter weights into logarithmic format, allowing for efficient logarithmic addition and accumulation operations, followed by format conversion back to floating point for further processing, thereby reducing computational overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating point data format is used for image data processing, then processing precision is maintained, but computational complexity and power consumption increase due to extensive format conversion
Solution Approach 1:
The patent transforms the data representation parameters from standard floating point format to logarithmic format. This parameter change allows multiplication operations to be performed as addition operations in the logarithmic domain, significantly reducing computational complexity while maintaining processing precision for image data processing tasks
2Measurement precision
If floating point data format is used for inferencing operations, then data accuracy is preserved, but power consumption increases due to extensive format conversion
Solution Approach 1:
The patent changes the numerical representation parameter from floating point to logarithmic format, enabling inferencing operations to be performed directly in logarithmic space. This eliminates the need for repeated format conversions between floating point and other formats, thereby reducing power consumption while preserving data accuracy through the mathematical properties of logarithmic transformation
3Adaptability or versatility
If standard floating point processing is used, then data format compatibility is maintained, but processing throughput decreases due to computational overhead
Solution Approach 1:
The patent transforms data to logarithmic format where arithmetic operations are simplified. Addition and subtraction in logarithmic space correspond to multiplication and division in linear space, reducing the number of computational steps required and increasing processing throughput while maintaining compatibility through configurable conversion interfaces
Solution Approach 2:
The patent replaces complex floating point arithmetic operations with simpler logarithmic domain operations. By substituting multiplication with addition and division with subtraction in the logarithmic domain, the computational overhead is reduced and processing throughput is improved
Data Source
AI summary
An integrated circuit including a plurality of logarithmic addition-accumulator circuits, connected in series, to, in operation, perform logarithmic addition and accumulate operations, wherein each logarithmic addition-accumulator circuit includes: (i) a logarithmic addition circuit to add a first input data and a filter weight data, each having the logarithmic data format, and to generate and output first sum data having a logarithmic data format, and (ii) an accumulator, coupled to the logarithmic addition circuit of the associated logarithmic addition-accumulator circuit, to add a second input data and the first sum data output by the associated logarithmic addition circuit to generate first accumulation data. The integrated circuit may further include first data format conversion circuitry, coupled to the output of each logarithmic addition circuit, to convert the data format of the first sum data to a floating point data format wherein the accumulator may be a floating point type.