Logarithmic Detector Pre-Charging for Faster RF Data Slicing

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Solution Overview

Problem

In RF receivers, especially low-frequency receivers for devices like remote controls and TPMS, existing analog circuits for demodulation and baseband processing often result in corrupted digital data signals due to noise and delayed extraction, as the averaging time constant compromises between speed and sensitivity.

Innovation Solution

A logarithmic detector is introduced, comprising detection stages and a summator to provide a logarithmic representation of the input signal, with pre-charging of an average filter using first and second pre-charge voltages based on carrier detection, allowing for efficient extraction of digital data signals by condensing the input dynamic range and optimizing the averaging process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If fast averaging is used in the average filter, then the delay in extracting digital data signal is reduced, but the ripple in the average signal increases which reduces sensitivity

Engineering Contradiction:
Improvedelay in extracting digital data signalVSAvoidsensitivity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-charging the average filter capacitor to a voltage corresponding to the average value of the input signal before data extraction begins. This initial charging eliminates the need for slow averaging to establish the baseline, allowing fast averaging to be used without sensitivity loss. The pre-charge voltage is determined by sampling the input signal and calculating its average value, then setting the capacitor voltage to match this average, thereby removing the trade-off between speed and sensitivity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If slow averaging is used in the average filter, then sensitivity is improved due to low ripple, but the delay in extracting valid digital data signal increases

Engineering Contradiction:
ImprovesensitivityVSAvoiddelay in extracting digital data signal
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent eliminates the need for slow averaging by performing the averaging function in advance through pre-charging the capacitor to the correct voltage level. This preliminary action provides the reference voltage immediately, allowing fast extraction of digital data without compromising sensitivity. The system achieves both fast response and high sensitivity by separating the averaging operation (done preliminarily) from the extraction operation (done rapidly).

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If analog circuits are used for demodulation and baseband processing, then the system is simpler, but the digital data signal becomes corrupted due to noise and the extraction is delayed

Engineering Contradiction:
Improvecircuit simplicityVSAvoidsignal accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent replaces the traditional analog averaging filter with a hybrid approach that uses a capacitor for storage but charges it based on digital processing of the input signal. The average value is calculated using digital logic that can filter noise effectively, then this clean digital-derived voltage is applied to the capacitor. This substitution of digital processing for analog filtering maintains circuit simplicity while eliminating noise corruption and extraction delay.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8750431B2Logarithmic detector and method of pre-charging an average filter on a logarithmic detector
Publication Date: 2014.06.10 NXP USA INC
  • US8750431B2 patent drawing
  • US8750431B2 patent drawing
  • US8750431B2 patent drawing

AI summary

The detector comprises a plurality of detection stages connected to a summator for providing a summation signal as a logarithmic representation of the input signal to a first input of a data slicer and an input of an average filter having an output connected to a second input of the data slicer. The data slicer has a data slicer output for providing an extracted digital data signal in dependence on a comparison of the summation signal and an output signal of the average filter. The average filter receives a first pre-charge voltage and a second pre-charge voltage depending on an output signal of a carrier detector circuit detecting a carrier signal of the input signal.