Logarithmic Power Detector Circuit for Linear-in-dB Response
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Solution Overview
Problem
Existing power detector circuits in CMOS IC technologies require large chip die area and consume significant current to achieve a linear response to signal power, as they are typically designed to produce an output voltage proportional to input voltage rather than power, necessitating multiple stages for approximation.
Innovation Solution
A power detector circuit with a wide dynamic range is implemented using a linear voltage-to-voltage detector followed by a true voltage-to-current-to-voltage converter with logarithmic current-to-voltage conversion, optimized gain distribution, and active resistance circuitry to minimize offset voltage and temperature sensitivity, achieving a linear-in-dB response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a typical power detector is designed to produce an output voltage proportional to input voltage, then the circuit design is simple, but the output is not linear with respect to signal power in dBm
Solution Approach 1:
The patent changes the functional parameter of the detector by implementing a true voltage-to-current-to-voltage converter that performs logarithmic current-to-voltage conversion, transforming the output characteristic from linear voltage proportionality to linear dBm response directly
Solution Approach 2:
The patent extracts and eliminates the need for multiple cascaded approximation stages by implementing a single-stage true logarithmic converter that directly produces the desired linear-in-dB response
2Manufacturing precision
If multiple cascaded stages are used to approximate linear-in-dB response, then the desired linearity is achieved, but chip die area consumption increases
Solution Approach 1:
The patent merges multiple cascaded stages into a single integrated voltage-to-current-to-voltage converter block that performs all necessary logarithmic conversion functions in one unified circuit, reducing the total chip area required
Solution Approach 2:
The patent changes the conversion mechanism from piece-wise approximation through multiple stages to a true logarithmic conversion in a single stage, achieving the same linearity goal with reduced area
3Measurement precision
If multiple cascaded stages are used to achieve linear-in-dB response, then the desired measurement precision is obtained, but current consumption increases
Solution Approach 1:
The patent combines multiple power-consuming stages into a single efficient voltage-to-current-to-voltage converter, reducing the total current draw while maintaining measurement precision through optimized gain distribution
Solution Approach 2:
The patent employs feedback mechanisms within the single-stage converter to maintain accuracy and linearity, eliminating the need for additional correction stages that would increase current consumption
4Ease of manufacture
If standard detector topology is used, then the circuit is easy to implement, but offset voltage from operational amplifiers corrupts the output voltage
Solution Approach 1:
The patent introduces an intermediary voltage-to-current conversion stage that isolates and manages offset voltage effects, preventing operational amplifier offsets from directly corrupting the final voltage output while maintaining implementation feasibility
Solution Approach 2:
The patent changes the intermediate representation parameter from voltage to current in the conversion stage, transforming offset voltage into offset current that can be more effectively managed and minimized in the subsequent logarithmic conversion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a power detector circuit that is chip die area efficient, consumes minimal current, and provides a linear output voltage response to input power, effectively addressing the limitations of prior art by optimizing linearity and mitigating error sources while compensating for temperature variations.
Implementation Method 1
The current-to-voltage conversion in the voltage-to-current-to-voltage converter is performed logarithmically. This construct generates a desired linear-in-dB response at the output.
Data Source
AI summary
A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.