Logarithmic Tree Modulo Units for Fast Integer Division
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Solution Overview
Problem
Conventional binary logic circuits for calculating the ratio x/d introduce significant latency and require large silicon area, as they either rely on inefficient long division or multiplication by a reciprocal, which are not optimal in terms of circuit area consumption or delay in the critical path.
Innovation Solution
A binary logic circuit utilizing a logarithmic tree of modulo units, arranged to calculate x[a: b]mod d for respective block positions, with output logic combining the outputs to yield the ratio x/d, minimizing delay and silicon area by optimizing the number and placement of modulo units within a delay envelope of [log2 M].
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If long division is used to calculate x/d, then silicon area consumption is reduced, but latency increases due to sequential operations
Solution Approach 1:
The input variable x is divided into M blocks of r bits each, and the division operation is segmented into multiple stages processing different block combinations. This allows parallel processing of segments while maintaining correctness, reducing overall latency without proportionally increasing silicon area.
Solution Approach 2:
The patent transforms the traditional sequential division approach into a multi-dimensional parallel structure by organizing modulo units in a tree-like hierarchy with multiple stages. Different stages process different block combinations simultaneously, effectively adding temporal and structural dimensions to the computation to achieve parallelism.
2Loss of time
If multiplication by reciprocal is used to calculate x/d, then latency is reduced, but silicon area consumption increases
Solution Approach 1:
The computation is segmented into modular units processing different block combinations, allowing selective parallelization. Not all possible combinations are computed simultaneously, but only those necessary for the final result, optimizing the balance between parallelism and resource usage.
Solution Approach 2:
The patent computes a subset of all possible block combinations rather than all M choose 2 combinations. The output logic selectively combines specific modulo unit outputs to produce the final result, performing only the necessary computations required for accuracy without redundant calculations.
3Measurement precision
If more modulo units are arranged at maximal delay to provide all x[0: m]mod d outputs, then calculation completeness is improved, but circuit area increases
Solution Approach 1:
Modulo units are designed to be multi-functional, where each unit can contribute to multiple different x[0: m]mod d outputs depending on the stage and combination. A single modulo unit processing blocks a:b can contribute to various final outputs through different combination paths in the output logic.
Solution Approach 2:
The patent provides exactly the necessary set of modulo unit outputs required for complete calculation, no more and no less. The output logic is designed to combine specific subset of modulo outputs to achieve all required x[0: m]mod d values with minimal redundancy.
Data Source
AI summary
A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0: m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of [log2 M]; and more than M−2u of the subset of modulo units are arranged at the maximal delay of [log2 M], where 2u is the power of 2 immediately smaller than M.