Logic Analyzer Bus Packet Format Display Method
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Solution Overview
Problem
Conventional logic analyzers struggle to display and analyze bus data that do not conform to standard specifications, making it difficult for users to understand and debug non-standard bus variables during development and debugging.
Innovation Solution
A bus packet format displaying method that converts unformatted bus packets into a formatted mode by defining a predetermined format for non-standard packet sections, dividing bits into message partitions, assigning message names, and displaying these on an operating screen, using a data format table, major index description table, and string table to provide meaningful values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional logic analyzer displays bus data without standard format specifications, then the display function is simple, but the user cannot understand the meaning of non-standard variables
Solution Approach 1:
The patent segments the bus packet into multiple sections including standard format sections and nonstandard format sections. Each section is processed separately with the nonstandard sections being divided into message partitions based on bit positions. This segmentation allows the system to handle complex nonstandard variables without overwhelming the entire display system, resolving the contradiction by breaking down the complex task into manageable parts.
Solution Approach 2:
The patent implements preliminary action by predefining format specifications for nonstandard bus variables before display. The system预先 defines message partitions, message names, and corresponding values for nonstandard packet sections. This preliminary structuring enables the logic analyzer to automatically interpret and display the meaning of nonstandard variables without requiring complex real-time analysis, thus reducing display complexity while preserving information.
2Ease of operation
If conventional logic analyzer displays all bus variables, then the display content is complete, but the user cannot easily observe and analyze the variables
Solution Approach 1:
The patent applies local quality by providing different display treatments for different parts of the bus packet. Standard format sections are displayed according to their standard specifications, while nonstandard sections are divided into message partitions with customized message names and values. This localized customization allows users to easily understand each variable's meaning without losing any packet details, as each section receives appropriate display treatment based on its specific characteristics.
Solution Approach 2:
The patent introduces message names and message values as intermediaries between the raw bus data and the user. For nonstandard packet sections, the system creates intermediate representations (message partitions with descriptive names and interpreted values) that bridge the gap between raw binary data and human-understandable information. This intermediary layer makes variable analysis easy while preserving the complete original data through the partitioning structure.
3Loss of information
If logic analyzer converts unformatted packets to formatted mode, then the user understanding is improved, but the processing time increases
Solution Approach 1:
The patent reduces processing time through preliminary action by predefining the format structure for nonstandard bus variables before actual packet analysis. The message partitions, message names, and value interpretations are prepared in advance based on the expected packet format. When packets are captured, the system can quickly map the raw data to the pre-defined structure without performing complex real-time analysis, thus improving user understanding while minimizing processing time overhead.
Data Source
AI summary
A bus packet format displaying method for a logic analyzer is disclosed. The logic analyzer fetches at least one packet of a bus of an electronic device. A computer host divides a plurality of bits of a second packet section of the packet into a plurality of message partitions according to a predetermined format defined in advance. Each of the message partitions has a value. The computer host gives a message name to each of the message partitions corresponding to the values and displays the message names and the values fetched by the logic analyzer on an operating screen.


