On-Chip Logic Analyzer With Centralized Trigger And Interleaved SRAM Capture
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Solution Overview
Problem
Debugging and testing of large integrated circuits are hindered by limited visibility of internal signals, inefficient sampling methods, and high costs associated with additional logic and wiring for observing internal nodes, as well as the difficulty in triggering and storing internal bus states.
Innovation Solution
An on-chip logic analyzer with centralized trigger logic and a single debug buffer that samples and stores signals from multiple internal nodes, allowing for efficient selection and storage of relevant signals using programmable registers and multiplexers, and enabling sampling at high rates without degrading chip performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If multiple local history buffers are added to capture internal bus signals, then more internal nodes can be observed, but the cost and complexity of the chip increases significantly
Solution Approach 1:
The patent merges multiple local history buffers into a single centralized debug buffer that serves all internal nodes. Instead of having separate buffers for each bus or node, one debug buffer captures signals from multiple sources sequentially, dramatically reducing the total number of buffer components needed on the chip.
Solution Approach 2:
The centralized debug buffer is designed to be universal, capable of capturing signals from any internal node or bus by being selectively connected to different sources. This multi-functional design allows a single buffer to replace what would traditionally require multiple dedicated buffers, reducing complexity while maintaining comprehensive observability.
2Loss of information
If scan chains are used to route internal nodes to external I/O, then internal signals become visible, but sampling cannot occur at full system speeds and requires time-consuming serial scan-out
Solution Approach 1:
The patent segments the signal capture function from the data output function. The debug buffer captures signals internally at full system speed independently of external scanning operations. This segmentation allows sampling to occur at maximum speed during normal operation, with data being scanned out separately at lower speeds without impacting the sampling rate.
Solution Approach 2:
The debug buffer performs preliminary capture of internal signals at full system speed before any external scanning occurs. By pre-capturing the data internally while the system operates at full speed, the buffer stores complete signal histories that can later be read out at slower scan rates without losing the high-speed sampling capability.
3Loss of information
If local history buffers are distributed throughout the chip, then triggering on internal events becomes more difficult without internal triggering mechanisms
Solution Approach 1:
The patent combines multiple distributed buffer control functions into a single centralized debug buffer with unified control logic. This centralization makes triggering easier because there is only one buffer to control rather than many distributed buffers, each requiring its own triggering mechanism. The centralized location allows for simpler trigger generation and management.
4Device complexity
If a single debug buffer is used to sample signals from multiple internal nodes, then the cost and complexity are reduced, but the buffer may need to operate at lower speeds to handle multiple signal sources
Solution Approach 1:
The patent employs periodic action by sequentially connecting the single debug buffer to different internal node sources in a time-multiplexed fashion. The buffer rapidly switches between capturing signals from different nodes in periodic cycles, allowing it to sample multiple sources at high effective rates without requiring parallel buffers for each source.
Solution Approach 2:
The debug buffer system is designed to be dynamic, with the buffer's input source being changeable over time rather than fixed. This dynamic reconfigurability allows the single buffer to adaptively connect to different internal nodes as needed, maintaining high sampling rates by efficiently time-multiplexing between sources rather than being constrained by a static, slower configuration.
Data Source
AI summary
A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.