On-Chip Logic Analyzer Event Triggers for Targeted Signal Capture
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Solution Overview
Problem
Current automatic test equipment (ATE) logic analyzers face challenges in efficiently capturing and analyzing signals from digital signal lines or logic chip pins, particularly in mixed-signal environments, where limited on-die space and varying clock frequencies complicate data capture and storage.
Innovation Solution
A programmable on-chip logic analyzer (POCLA) with an event-trigger state machine and programmable filter modules that selectively capture and store signal states based on programmable events and conditions, allowing for efficient data analysis and storage of targeted data, even in high-speed environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional logic analyzers capture all signals from digital signal lines, then complete data coverage is achieved, but on-die space is excessively consumed
Solution Approach 1:
The patent extracts and stores only the essential identification information (signature data) of captured vectors in a compact signature register, rather than storing complete capture vectors. This extraction principle reduces the storage burden while maintaining the ability to identify and analyze relevant signal patterns, thereby achieving complete data coverage with minimal on-die space consumption.
Solution Approach 2:
The patent segments the signal analysis function into multiple independent logic analyzer units, each capable of autonomous operation with its own capture and comparison capabilities. This segmentation allows distributed analysis across different signal domains, reducing the need for centralized large-capacity storage and enabling efficient use of limited on-die space through localized processing.
2Loss of information
If logic analyzers store complete capture vectors for analysis, then detailed signal information is preserved, but storage capacity is quickly exhausted
Solution Approach 1:
The patent extracts only the critical identification features of captured vectors and stores them in compact signature registers. By taking out only the essential information needed for pattern recognition and analysis, the system preserves sufficient signal information for debugging while dramatically reducing the quantity of stored data, thus avoiding storage capacity exhaustion.
Solution Approach 2:
Instead of storing complete vectors and then analyzing them, the patent inverts the approach by first extracting signature characteristics and storing only those, then performing analysis on the compact representations. This inversion eliminates the need for large storage capacity while maintaining analytical effectiveness.
3Speed
If logic analyzers operate at high clock frequencies, then high-speed signal capture is achieved, but timing synchronization becomes more difficult
Solution Approach 1:
The patent divides the high-speed signal capture function into multiple independent logic analyzer units, each operating autonomously at the required clock frequency. This segmentation isolates timing synchronization requirements to individual units, preventing system-wide synchronization complexity while enabling high-speed operation through parallel independent processing.
Solution Approach 2:
The patent performs preliminary capture of signal states at each clock cycle and immediately processes them through comparison logic before proceeding to the next cycle. This preliminary action at high frequency eliminates the need for complex post-capture timing synchronization, as the timing relationships are preserved in the sequential capture process itself.
Data Source
AI summary
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.