Logic Analyzer Trace Capture for Fixed-Length Signal Compression
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Solution Overview
Problem
The data size of monitor target signals in logic analyzer circuits increases proportionally with the number of changed signals per time stamp, particularly in formats like VCD, making efficient verification and data transfer challenging.
Innovation Solution
A logic analyzer circuit with a trace capture circuit and buffer that stores signal data in a binary format with fixed length, combined with compression algorithms like run-length encoding and Huffman coding, to reduce data size and enable efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If VCD format with ASCII encoding is used to record signal state changes, then human readability and compatibility are improved, but data size increases proportionally with the number of changed signals per time stamp
Solution Approach 1:
The patent changes the encoding parameter from ASCII text format to binary format. Each signal state change is represented by a fixed 2-byte binary structure (1 byte timestamp + 1 byte signal value), reducing data size from variable-length ASCII strings to compact binary representations. This parameter change directly resolves the contradiction by maintaining full information while minimizing data volume.
Solution Approach 2:
The patent applies different representation methods to different parts of the data structure. The timestamp uses compact binary encoding while the signal value uses differential encoding (change detection). This local optimization of encoding quality for different data elements achieves overall data size reduction while preserving necessary information.
2Loss of information
If continuous sampling of signal values is performed, then complete signal information is captured, but data size and processing load increase significantly
Solution Approach 1:
The patent extracts only the essential information from continuous signals - specifically, only state changes are recorded rather than continuous values. The trace capture circuit detects transitions and records only those moments when signal states change, eliminating redundant data while preserving all meaningful information for logic analysis.
Solution Approach 2:
Instead of continuous sampling, the system uses event-triggered periodic recording where data is captured at discrete moments when state changes occur. This periodic action based on change detection rather than time intervals reduces data volume while maintaining complete information about signal behavior.
3Adaptability or versatility
If a large number of internal signals are monitored simultaneously, then verification coverage is improved, but data transfer time and processing complexity increase
Solution Approach 1:
The patent changes the data representation parameter to fixed-length binary format, which enables efficient bulk data transfer and processing. The uniform 2-byte structure for each signal change event allows for optimized memory access patterns, faster serialization/deserialization, and reduced processing overhead compared to variable-length ASCII formats, thereby improving productivity despite increased verification coverage.
Data Source
AI summary
A logic analyzer circuit includes a trace capture circuit to acquire N observation target signals from an observation target circuit when there is change in at least one of the N observation target signals and a buffer where signal data acquired by the trace capture circuit is stored. The signal data has a time stamp of an M-bit width indicating time of acquisition and state change data of an N-bit width corresponding to respective values of the N observation target signals. The signal data is data in a binary format having a fixed length of (M+N) bits.