Variable-Topology Logic Array With Constant Power Signatures
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Solution Overview
Problem
Conventional computing systems face inefficiencies due to static logic gate configurations, high overhead in FPGA technology, and challenges in implementing chaotic circuits using integrated circuits, which result in unused circuitry and increased costs.
Innovation Solution
A universal logic array with variable topology and chaotic cell design that utilizes logistic mapping functions, allowing for dynamic reconfiguration and reduced power dissipation, enabling the realization of any logic combination with fewer transistors and improved security through constant power signature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA technology is used to support any application through electrical programming, then adaptability is improved, but device complexity and overhead increase to 80-90% of total die area
Solution Approach 1:
The patent implements a universal logic array where identical basic logic cells can be configured to perform multiple different logic functions through electrical programming of connection states. Each logic cell contains transistors that can be programmed to implement AND, OR, NOT, NAND, NOR, XOR, or other logic functions, eliminating the need for dedicated hardware for each function type while maintaining adaptability across applications
Solution Approach 2:
The patent merges multiple logic functions into a single reconfigurable logic cell structure. By combining the logic implementation and interconnect functionality into unified programmable cells, the design reduces the separation between logic blocks and routing resources that typically consumes 80-90% overhead in traditional FPGAs, achieving more efficient resource utilization while preserving application flexibility
2Adaptability or versatility
If all field-programmable circuit elements are fixed in size and structure to support multiple applications, then adaptability is improved, but productivity decreases due to unused circuitry
Solution Approach 1:
The patent implements dynamically reconfigurable logic cells where the circuit topology and transistor connections can be changed during operation through electrical programming signals. This dynamic reconfiguration allows the same physical silicon area to be optimized for different logic functions and application requirements, maximizing silicon utilization while maintaining multi-application support capability
Solution Approach 2:
The patent changes the electrical parameters and connection states of the logic cell transistors through applied programming voltages. By modifying the conductive states and interconnect configurations of the same physical structures, the system achieves different logic functions without requiring additional silicon area, thereby improving productivity through better silicon utilization while preserving adaptability
3Adaptability or versatility
If chaotic circuits are implemented using traditional integrated circuit technology with inductors and capacitors, then non-linear behavior is achieved, but area consumption increases significantly
Solution Approach 1:
The patent replaces traditional mechanical/physical chaotic circuit elements (inductors, capacitors, operational amplifiers) with transistor-based electronic implementations using standard CMOS technology. The chaotic non-linear behavior is achieved through the inherent non-linear characteristics of MOSFET transistors operating in specific regions, eliminating the need for large-area passive components while preserving the desired chaotic dynamics capability
Solution Approach 2:
The patent achieves chaotic behavior by changing the operating parameters and bias conditions of the transistor circuits rather than relying on large passive components. By adjusting transistor dimensions, bias voltages, and interconnect configurations, the system generates chaotic dynamics using minimal silicon area compatible with standard integrated circuit fabrication processes
Data Source
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AI summary
Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.