Logic-Based Read Sample Offset Circuit for Memory Subsystems
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Solution Overview
Problem
Conventional memory sub-systems rely on Error Correction Code (ECC) decoders to perform read sample offset operations, which are limited by the correction capability of the ECC decoder, and require multiple read operations to determine difference bit counts, making them inefficient for handling a large number of bit errors.
Innovation Solution
Implementing a logic-based read sample offset operation using exclusive-or (XOR) operations to determine difference bit counts without the need for ECC decoders, allowing for concurrent or simultaneous read level threshold operations and enabling additional operations like continuous read level calibration and dynamic program targeting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC decoders are used to perform read sample offset operations, then error correction capability is maintained, but the system is limited by the correction capability of the ECC decoder and requires multiple read operations making it inefficient for handling large numbers of bit errors
Solution Approach 1:
The patent extracts the read sample offset operation from the ECC decoder framework. Instead of relying on ECC decoders to perform read sample offset operations, the invention implements a dedicated read sample offset circuit that operates independently, thereby removing the limitation of ECC correction capability and enabling efficient handling of large numbers of bit errors.
Solution Approach 2:
The patent segments the error handling function by separating read sample offset operations from ECC decoding. The read sample offset circuit processes offset operations independently while ECC decoding handles correction, allowing each component to specialize and improving overall efficiency for handling bit errors beyond ECC capabilities.
2Measurement precision
If multiple read operations are performed to determine difference bit counts, then accurate error measurement is achieved, but the process becomes time-consuming and inefficient
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing read sample offset values in lookup tables during manufacturing or initialization. During operation, the circuit directly retrieves pre-computed difference bit counts from these tables based on read levels and offsets, eliminating the need for multiple sequential read operations and significantly reducing measurement time while maintaining accuracy.
Solution Approach 2:
The patent uses copying by storing pre-computed difference bit count values in lookup tables. Instead of performing multiple read operations to determine difference bit counts, the system copies pre-calculated values from the lookup tables based on current read levels and offsets, achieving both accuracy and speed.
3Reliability
If ECC decoders are used for read sample offset operations, then error correction is provided, but additional operations like continuous read level calibration and dynamic program targeting cannot be performed
Solution Approach 1:
The patent implements universality by designing a read sample offset circuit that serves multiple functions: it performs read sample offset operations, enables continuous read level calibration, supports dynamic program targeting, and provides difference bit count determination. This multi-functional circuit replaces the limited ECC decoder approach and enables various advanced operations beyond basic error correction.
Solution Approach 2:
The patent applies dynamics by enabling continuous read level calibration and dynamic program targeting operations. The read sample offset circuit can dynamically adjust read levels and program targets based on real-time measurements, providing adaptability and versatility that static ECC decoder-based systems cannot achieve.
Data Source
AI summary
The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.