Programmable Logic Block with Flexible Per-Cell Clock Selection
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Solution Overview
Problem
Traditional programmable logic array (PLA) systems lack flexibility in selecting a clock signal, resulting in static and inflexible designs, and often offer either low complexity or high complexity options without intermediate flexibility.
Innovation Solution
The proposed PLA system allows for great flexibility in selecting clock sources by making a global PLA clock signal available to each logic cell, and enabling each logic cell to use one of its input signals as a clock signal, which can be selected during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single global clock signal is supplied to all flip-flops in a traditional PLA system, then synchronization and reliability are improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The patent divides the unified clock distribution system into segmented clock sources at each logic cell level. Each logic cell can independently select its clock source from multiple options (global clock, local input signals, or other logic cell outputs), creating a hierarchical segmentation that maintains system-wide synchronization while enabling local flexibility.
Solution Approach 2:
The patent introduces dynamic clock selection capability where the clock source for each logic cell can be programmatically configured and changed. This transforms the static, fixed clock distribution of traditional PLAs into a dynamic system that can adapt clock sources based on specific application requirements, resolving the contradiction between reliability and flexibility.
2Device complexity
If traditional PLA systems use a fixed clock distribution architecture, then device complexity is reduced, but adaptability and programmability worsen
Solution Approach 1:
The patent makes input signals of each logic cell universally available as potential clock sources, in addition to the global clock signal. This multi-functionality allows the same input signal to serve either as data input or as a clock source depending on configuration, increasing adaptability without significantly increasing architectural complexity.
Solution Approach 2:
Each logic cell is equipped with the capability to independently select and configure its own clock source from available options. This self-service approach allows local adaptation and customization without requiring complex centralized control, maintaining architectural simplicity while enhancing programmability.
3Manufacturing precision
If either low complexity PLA or high complexity FPGA is provided, then manufacturing precision is maintained, but adaptability to different user needs deteriorates
Solution Approach 1:
The patent enables continuous parameter adjustment of clock distribution characteristics by allowing selection among multiple clock sources with different frequencies and phases. Users can programmatically change clock parameters (source selection, timing) to match specific application requirements, providing intermediate flexibility between traditional PLA and FPGA without sacrificing implementation precision.
Data Source
AI summary
An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.