Reconfigurable Logic Block for Verified Partial Reconfiguration
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Solution Overview
Problem
Conventional Programmable Logic Devices (PLDs) are limited in their ability to store both a design state and a user-defined state concurrently, and they struggle with reconfiguration while operational, leading to limitations in implementing logic circuits.
Innovation Solution
A programmable logic device with a logic block and configuration logic that includes a mode flag and an enable read flag, allowing the configuration logic to be excluded or included in data verification and correction processes based on the stored state, enabling concurrent storage of design and user-defined states without verification errors and facilitating dynamic reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration logic is included in data verification and correction processes, then design state storage is reliable, but user-defined state storage cannot be maintained concurrently
Solution Approach 1:
The configuration logic is segmented into two distinct storage paths: one for design state (subject to verification and correction) and one for user-defined state (excluded from verification). The mode flag and enable read flag work together to route configuration data to the appropriate storage path, allowing both design state reliability and user-defined state versatility to coexist
Solution Approach 2:
The system dynamically switches between including and excluding configuration logic from verification processes based on the mode flag setting. When in user-defined state mode, the enable read flag prevents verification and correction processes from accessing configuration logic, allowing flexible reconfiguration while maintaining design state integrity when needed
2Adaptability or versatility
If PLD operates as user RAM, then user-defined state is stored, but verification and correction processes cannot access configuration logic
Solution Approach 1:
The enable read flag acts as an intermediary control mechanism that mediates between user RAM operation and verification processes. When set, it prevents verification and correction processes from accessing configuration logic, ensuring user-defined state integrity. When cleared, it allows verification to proceed for design state operations
3Productivity
If reconfiguration is performed while PLD is operational, then system availability is maintained, but verification errors may occur
Solution Approach 1:
The system dynamically adjusts verification behavior based on operational state. During reconfiguration operations, the mode flag and enable read flag work together to exclude configuration logic from verification processes, preventing verification errors while maintaining continuous operation. When reconfiguration is complete, verification can be re-enabled to ensure integrity
Data Source
AI summary
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.