Programmable Logic Block RAM Bypass for Lower Write Output Delay
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in achieving improved output delay and efficiency when functioning as random access memory (RAM), particularly due to the complexity of memory array and multiplexer structures.
Innovation Solution
A programmable logic block is designed with memory cells, a multiplexer structure, a bypass select multiplexer, and a control circuit that allows bypassing the memory array and multiplexer structure when writing new values to RAM, enabling simultaneous writing to both the RAM and a memory element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the conventional memory array and multiplexer structure is used for RAM write operations, then the device can maintain its programmable logic functionality, but the output delay is increased and writing efficiency is reduced
Solution Approach 1:
The patent segments the write path into two independent channels: a conventional path through the memory array and multiplexer structure, and a bypass path directly to the memory element. This segmentation allows the system to choose the optimal path based on operational requirements, reducing output delay when using the bypass path while maintaining the conventional structure for other operations.
Solution Approach 2:
The bypass select multiplexer acts as an intermediary component that directs the write data input signal either to the memory array (conventional path) or directly to the memory element (bypass path). This intermediary enables fast write operations by routing data through the shortest path while preserving the functionality of the conventional memory structure.
2Productivity
If data is written through the conventional memory array and multiplexer structure, then the RAM can store new values, but the writing speed and efficiency are reduced due to the complex signal path
Solution Approach 1:
The patent extracts the essential write function from the complex memory array and multiplexer structure by creating a direct bypass path. This extraction removes the unnecessary intermediate steps (memory array access and multiplexer selection) from the critical write path, significantly improving writing efficiency while keeping the original structure intact for other operations.
Solution Approach 2:
Instead of following the conventional path where write data must pass through the memory array and multiplexer structure, the patent inverts the approach by providing a direct path from the write data input signal to the memory element. This inversion of the signal flow path eliminates the bottlenecks in the conventional structure and improves writing speed.
3Speed
If the bypass path is used for RAM write operations, then the output delay is reduced and writing efficiency is improved, but the conventional memory array structure is bypassed
Solution Approach 1:
The patent implements a dynamic write path selection mechanism where the bypass select multiplexer can switch between the conventional path and the bypass path based on operational requirements. This dynamic adaptability allows the system to use the fast bypass path for time-critical write operations while maintaining the capability to use the conventional path for other operations, thus preserving versatility.
Solution Approach 2:
The write input circuit is designed with multi-functionality to support both conventional RAM write operations (through the memory array and multiplexer structure) and fast write operations (through the bypass path). This universal design allows the same hardware structure to serve multiple purposes: maintaining backward compatibility with conventional operations while enabling improved performance when needed.
Data Source
AI summary
A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.