Logic Block Segmentation for Routing Congestion
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Solution Overview
Problem
Conventional digital circuit logic blocks often experience wiring congestion due to inputs and outputs being centrally located, leading to increased adjacency capacitance and noise, which hinders wirability and timing performance.
Innovation Solution
The method involves transforming a logic block into a two-stage structure with an input stage and an output stage, where inputs and outputs are grouped into proximate sets, and each gate is placed in close proximity to its respective inputs or outputs, reducing congestion by distributing signal handling across multiple gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If logic block is placed at central area surrounded by inputs and outputs, then signal routing is simplified, but wiring congestion increases
Solution Approach 1:
The logic block is divided into multiple clusters, with each cluster handling a subset of inputs and outputs. This segmentation distributes the wiring load across different spatial regions, preventing congestion in any single area while maintaining organized signal routing pathways.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional clustered arrangement. By organizing logic elements into vertical and horizontal clusters that extend in multiple spatial dimensions, the design accommodates more connections without increasing congestion in any single plane.
2Adaptability or versatility
If logic block is placed at central area, then connectivity is improved, but adjacency capacitance increases
Solution Approach 1:
By segmenting the logic block into distributed clusters rather than a single centralized unit, the patent reduces the density of adjacent signaling elements. This lowers mutual capacitance effects between nearby wires and logic elements while preserving overall connectivity through the clustered architecture.
Solution Approach 2:
Each cluster is designed with local optimization for its specific set of inputs and outputs, allowing wiring patterns to be tailored to minimize local capacitance effects. The local quality of each cluster's layout can be optimized independently to reduce adjacency capacitance while maintaining the cluster's connectivity function.
3Ease of operation
If logic block is placed at central area, then signal distribution is simplified, but noise increases
Solution Approach 1:
Segmenting the logic block into separate clusters physically isolates different signal paths, reducing crosstalk and noise interference between adjacent signals. Each cluster can be routed independently, allowing noise-sensitive signals to be placed in clusters away from high-switching-activity elements.
Solution Approach 2:
The clustered architecture introduces intermediate routing layers and buffer elements between different logic clusters. These intermediaries act as isolation barriers that prevent noise propagation from one cluster to another while maintaining signal distribution functionality.
Data Source
AI summary
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.