Logic Brick Layout for Fewer Transistors and Geometry Patterns
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Solution Overview
Problem
Integrated circuit design faces challenges in minimizing the number of transistors and unique geometry patterns, which can lead to increased area and performance penalties due to the need for regularity in manufacturing.
Innovation Solution
A method and system for grouping logic into macro-regular 'bricks' that implement non-standard complex Boolean logic functions, using techniques such as minimal negative gate algorithms and recursive decomposition to reduce the number of transistors and optimize layout, thereby minimizing the number of unique geometry patterns required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If logic is grouped into macro-regular bricks to improve manufacturability, then manufacturing precision is improved, but device complexity increases due to non-standard complex Boolean logic functions
Solution Approach 1:
The patent segments complex Boolean logic functions into smaller sub-functions that can be implemented using standard logic cells. The logic brick is divided into multiple stages, where each stage implements a subset of the overall logic function, allowing complex functions to be broken down into manageable pieces that maintain regularity and manufacturability
Solution Approach 2:
The patent implements a hierarchical structure where logic bricks are nested within larger logic structures. Each logic brick contains multiple logic cells that are nested in a regular pattern, with push rules nested within the brick definitions. This nested organization allows complex functions to be built from simpler, regularly-structured components
2Area of stationary object
If transistor count is reduced to improve area efficiency, then area is improved, but reliability may worsen due to fewer transistors available for implementing logic functions
Solution Approach 1:
The patent changes the structural parameters of logic implementation by introducing logic bricks with specific stack heights and multiple logic cells per brick. This allows the same logic function to be implemented with fewer total transistors while maintaining reliability through the distributed architecture across multiple cells and stages
Solution Approach 2:
The patent creates universal logic bricks that can implement multiple different Boolean logic functions using the same physical structure. A single brick design with configurable push rules can realize various logic functions, reducing the need for multiple specialized transistor implementations and improving area efficiency while maintaining functional reliability
3Ease of manufacture
If stack depth is restricted to no more than 3 to simplify layout, then ease of manufacture is improved, but device complexity increases for functions requiring deeper stacks
Solution Approach 1:
The patent segments deep logic stacks into multiple smaller stacks of depth 3 or less by introducing intermediate logic cells. Instead of implementing a single deep stack, the logic function is divided across multiple stages, each with limited stack depth, connected through intermediate logic cells that maintain the overall function while simplifying the physical layout
Solution Approach 2:
The patent resolves the stack depth constraint by transitioning from a vertical dimension solution to a horizontal dimension solution. Instead of stacking transistors vertically beyond depth 3, the logic function is expanded horizontally across multiple logic cells and stages, maintaining the same logical depth through additional spatial dimensions in the layout
4Manufacturing precision
If the number of unique geometry patterns is reduced to improve manufacturing regularity, then manufacturing precision is improved, but adaptability worsens for implementing diverse logic functions
Solution Approach 1:
The patent creates universal logic brick templates that can implement multiple different Boolean logic functions using the same geometry patterns. By configuring the push rules and logic cell interconnections within the standardized brick structure, diverse logic functions can be realized without introducing new geometry patterns, maintaining manufacturing regularity while achieving functional versatility
Solution Approach 2:
The patent introduces dynamic configurability within the standardized logic brick structure through programmable push rules and configurable logic cell connections. This allows the same physical geometry to adapt to different logic function requirements by changing the logical configuration rather than the physical structure, maintaining regularity while providing adaptability
Data Source
AI summary
A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.