Logic Cell Clock Gating to Prevent Spurious Internal Toggling
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Solution Overview
Problem
Existing integrated circuit logic circuits continue to consume power unnecessarily due to spurious toggling at internal nodes when in set or reset modes, despite existing power reduction techniques, as these nodes receive clock signals even when not needed.
Innovation Solution
The integration of gated clocking circuitry within logic cells that monitors and responds to predetermined logic states, effectively turning off clock nodes during set or reset modes to prevent unnecessary toggling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are continuously provided to logic cells, then logic circuits can respond to input changes, but unnecessary toggling occurs at internal nodes during set or reset modes consuming excess power
Solution Approach 1:
The clocking circuitry dynamically adjusts the clock signal distribution based on the logic cell's operational state. When in set or reset modes, the clocking circuitry gates off clock signals to internal nodes that do not require updating, while maintaining clock signals to nodes that must track input changes. This dynamic adaptation eliminates unnecessary toggling and power consumption while preserving circuit responsiveness.
Solution Approach 2:
Different internal nodes within the logic cell receive different clocking treatments based on their specific functional requirements. Nodes directly controlled by the clock receive continuous signals, while other nodes receive gated clock signals that are suppressed during set or reset modes. This localized differentiation allows the circuit to maintain reliability where needed while reducing power consumption in areas where it is unnecessary.
2Loss of energy
If clocking circuitry is added to gate internal clock nodes, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The clocking circuitry is merged with the existing logic cell structure, sharing physical space and functional integration rather than being a separate added component. The clock gating logic is combined with the set/reset logic and internal node control, allowing the same circuit elements to serve multiple functions. This merging approach minimizes the additional complexity introduced by power reduction features.
Solution Approach 2:
The clocking circuitry is designed to perform multiple functions: it distributes clock signals to internal nodes, gates clock signals during set/reset modes, and maintains circuit operation during normal modes. By making the clocking circuitry multi-functional, the patent reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving power reduction goals.
Data Source
AI summary
A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.