Sequential Logic Cell Circuit Without Complement Clock Writing
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Solution Overview
Problem
Existing sequential logic cells in CMOS technology require the complement of the control signal for data writing, leading to increased power consumption and complexity, and are vulnerable to soft-errors due to the need to overwrite prior values during data switching.
Innovation Solution
A new connection method for the control and data signals in sequential logic cells that uses only the primary control signal, disconnects the original cross-coupled INV pair during data writing, and incorporates additional MOSFETs to facilitate data switching without requiring the complement signal, thereby reducing power consumption and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the complement of the control signal is used for data writing in sequential logic cells, then data switching can be accomplished, but power consumption increases and circuit complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for the complement control signal from the sequential logic cell operation. By using only the primary control signal (CK) to gate the data input (D) directly to the cross-coupled inverters, the circuit removes the requirement for generating and using the complement signal (CKB), thereby reducing power consumption and circuit complexity while maintaining data switching capability.
Solution Approach 2:
The primary control signal CK serves multiple functions: it acts as the clock signal for timing operations and simultaneously functions as the gate control for data input. This multi-functionality eliminates the need for a separate complement signal, reducing overall circuit complexity and power consumption while maintaining full data switching capability.
2Reliability
If the complement of the control signal is used for data writing, then data switching can be accomplished, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for the complement control signal from the sequential logic cell operation. By using only the primary control signal (CK) to gate the data input (D) directly to the cross-coupled inverters, the circuit removes the requirement for generating and using the complement signal (CKB), thereby reducing power consumption and circuit complexity while maintaining data switching capability.
Solution Approach 2:
The patent merges the clock function and data gate control function into a single primary control signal CK. This signal simultaneously provides the timing clock edge and controls the gating of data input to the storage element, eliminating the need for separate complement signal generation circuitry and reducing overall device complexity.
3Productivity
If prior data values are overwritten during data switching, then new data can be written, but vulnerability to soft-errors increases
Solution Approach 1:
The patent applies preliminary action by disconnecting the data input path from the cross-coupled inverters during the write operation. The control signal CK gates the data input D through transmission gates to the inverter inputs, and when CK transitions, the new data is written without requiring complete overwriting of prior values, thereby reducing vulnerability to soft-errors while maintaining data writing capability.
4Reliability
If additional MOSFETs are added to disconnect cross-coupled INV pair during data writing, then power consumption is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The control signal CK serves multiple functions: it acts as the clock signal for timing operations and simultaneously functions as the gate control for data input. This multi-functionality eliminates the need for a separate complement signal, reducing overall circuit complexity and power consumption while maintaining full data switching capability.
Solution Approach 2:
Transmission gates controlled by the primary signal CK act as intermediaries between the data input and the cross-coupled inverters. These transmission gates enable controlled connection and disconnection of the data path, allowing new data to be written while isolating the storage element from potential soft-error sources, thereby improving reliability without requiring complex additional circuitry.
Data Source
AI summary
This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.