Complex Logic Cell Decomposition for Reduced Processing Time

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Solution Overview

Problem

Current cell characterization processes for electronic circuits are computationally intensive, especially for complex logic cells with multiple components, leading to inefficiencies and excessive processing times.

Innovation Solution

A system and method that decompose complex logic cells into channel-connected component portions, generate component characteristic functions, and expand these functions to exclude irrelevant nodes, allowing for computationally manageable logical expansions and reduced processing times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If cell characterization processes are applied to complex logic cells with multiple components, then complete electrical and logical behavior extraction is achieved, but processing time and computational load become excessively high

Engineering Contradiction:
Improvebehavior extraction completenessVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The logic cell is decomposed into multiple channel-connected component (CCC) portions, each representing a subset of the total logic components. This segmentation allows the characterization process to be divided into smaller, more manageable tasks that can be processed independently and in parallel, significantly reducing the overall computational burden and processing time while maintaining complete behavior extraction through the systematic combination of CCC results.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If logical expansion is performed on complex logic cells, then comprehensive node analysis is achieved, but computational complexity becomes unmanageable

Engineering Contradiction:
Improvenode analysis completenessVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Logical expansion is performed separately on each CCC portion rather than on the entire logic cell at once. Each CCC undergoes independent logical expansion to identify its relevant nodes and vectors, and the results are then combined systematically. This segmented approach reduces the computational complexity of each expansion operation while ensuring comprehensive node analysis through the aggregation of all CCC results.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method extracts and identifies only the electrically relevant nodes within each CCC portion during logical expansion, filtering out extraneous nodes that do not contribute to the electrical behavior. This extraction process reduces the number of nodes requiring detailed analysis while maintaining completeness of the relevant behavioral characterization.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If extraneous nodes are included in logical representation, then complete node coverage is achieved, but processing efficiency decreases due to unnecessary analyses

Engineering Contradiction:
Improvenode coverage completenessVSAvoidprocessing efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The method extracts and retains only the electrically relevant nodes within each CCC portion, systematically identifying and excluding extraneous nodes that do not affect the electrical or logical behavior. This selective retention maintains complete coverage of all nodes that contribute to the cell's behavior while eliminating unnecessary analyses, thereby significantly improving processing efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each CCC portion is analyzed with focused attention on its local electrical relevance, identifying nodes that are electrically connected within that specific portion. This local quality approach ensures that each CCC undergoes analysis appropriate to its scope, avoiding the inefficiency of applying uniform comprehensive analysis to all nodes regardless of their actual electrical significance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10133835B1System and method for computationally optimized characterization of complex logic cells
Publication Date: 2018.11.20 CADENCE DESIGN SYST INC
  • US10133835B1 patent drawing
  • US10133835B1 patent drawing
  • US10133835B1 patent drawing

AI summary

A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of vectors for nodes electrically connected to the local output node. Each CCC's component characteristic function is expanded to form a local characteristic function relative to one or more other upstream CCC. Each local characteristic function is thereby formed exclusive of any upstream local output node electrically disconnected from its local output node. At least one feasible vector is selectively generated from the local characteristic functions according to requirements predefined for a parametric measurement.