Logic Cell Layout With Hybrid Fillers for Mixed Cell Heights
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration and performance due to differences in design rules and cell heights between logic cells, leading to inefficiencies in space utilization and operational speed.
Innovation Solution
The semiconductor device incorporates a hybrid filler cell and wrapper structures to compensate for differences in cell heights and design rules between logic cells, allowing for increased integration and performance by optimizing the arrangement of power lines and active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If logic cells with different cell heights are used to achieve high integration, then space utilization improves, but differences in design rules and cell heights lead to inefficiencies in space utilization and operational speed
Solution Approach 1:
The patent applies local quality by creating different cell height regions within the same semiconductor device. First logic cells have a first cell height while second logic cells have a second cell height different from the first. This allows each region to be optimized for its specific function: higher integration in some areas and high-speed operation in others, resolving the contradiction between integration density and operational speed.
2Quantity of substance
If hybrid filler cells are used to compensate for cell height differences, then space utilization improves, but device complexity increases
Solution Approach 1:
Hybrid filler cells serve as intermediary structures between first logic cells and second logic cells with different cell heights. These filler cells compensate for the height differences and enable proper electrical connections and signal routing between cells of different heights, thus improving space utilization while managing the complexity through a standardized intermediary approach.
3Productivity
If wrapper structures are used to optimize power line arrangement, then performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into different cell types (first logic cells, second logic cells, and hybrid filler cells) with distinct structures and functions. This segmentation allows wrapper structures to be selectively applied to specific cell regions where performance optimization is needed, rather than throughout the entire device, thus balancing performance improvement with manufacturing feasibility.
Data Source
AI summary
Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.