Logic Cell Interconnect Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical characteristics and reliability.
Innovation Solution
The semiconductor device includes a first and second logic cell with specific interconnection line configurations and fabrication methods involving mold layer etching and spacer formation to achieve precise interconnection line spacing and protrusions, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacked interconnection layers. Multiple interconnection lines are arranged vertically across different metal layers (first metal layer, second metal layer, third metal layer) to achieve higher integration density without further reducing the lateral pattern size of MOSFETs.
Solution Approach 2:
The interconnection structure is segmented into multiple independent metal layers with distinct interconnection lines in each layer. This segmentation allows independent routing and spacing control for each layer, enabling precise spacing (12-18 nm) to be maintained while achieving high density through vertical stacking.
2Productivity
If interconnection lines are placed closer together to increase density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Mandrel patterns are formed first as templates before depositing spacer materials. The spacers are then formed conformally on the mandrels and anisotropically etched to create the final interconnection lines. This preliminary mandrel formation establishes precise spacing geometry before the actual interconnection structure is built.
Solution Approach 2:
Spacer materials serve as intermediaries that define the final interconnection line positions and spacing. The spacers are deposited conformally on mandrel patterns and then selectively removed, leaving precisely spaced interconnection lines with controlled pitch (12-18 nm) that would be difficult to achieve directly through lithography alone.
3Reliability
If protrusions are added to interconnection lines to enhance connectivity, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
Interconnection lines in upper metal layers are positioned to overlap with and nest around interconnection lines in lower layers. The protrusions of interconnection lines extend vertically to overlap with contacts or vias in adjacent layers, creating nested three-dimensional interconnection structures that enhance electrical connectivity without requiring additional lateral space.
Data Source
AI summary
A semiconductor device may include first and second logic cells, which are on a substrate and are spaced apart from each other in a first direction, and each of which includes PMOSFET and NMOSFET regions, and first and second metal layers on the first and second logic cells, respectively. The first metal layer may include first, second, and third right interconnection lines, which extend in the first direction parallel to each other, with the second right interconnection line between the first and third right interconnection lines. The second metal layer may include a first left interconnection line. A shortest distance between the first right interconnection line and the first left interconnection line in the first direction may be defined as a first distance that is in a range from 12 nm to 18 nm.