Customizable Logic Cell for BEOL Logic Inversion Correction
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Solution Overview
Problem
Existing integrated circuit (IC) manufacturing processes face issues with logic inversion errors, where inverting gates function incorrectly, requiring re-manufacturing of BEOL layers or adding logic-controlled inverters, which cause timing delays and occupy additional surface area.
Innovation Solution
A customizable logic cell structure comprising complementary transistors connected in series with configurable gate couplings and BEOL layers, allowing correction of logic inversion errors without re-manufacturing by adjusting voltage node connections in later manufacturing phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic inversion errors are corrected by re-manufacturing BEOL layers, then logic inversion errors are corrected, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent incorporates preliminary correction mechanisms during the device layer formation stage by integrating controllable inverter structures that can be activated later via BEOL layer configurations. This preliminary setup allows error correction without requiring complete re-manufacturing of BEOL layers, thus reducing manufacturing time while maintaining reliability
Solution Approach 2:
The patent introduces intermediate controllable inverter structures between the logic gates and output lines that act as mediators. These intermediaries can be selectively activated through BEOL layer connections to correct logic inversion errors without requiring re-manufacturing of the entire BEOL structure, thereby resolving the contradiction between error correction and manufacturing time
2Reliability
If logic-controlled inverters or buffers are integrated into the device structure to correct logic inversion, then logic inversion errors are corrected, but timing delays increase
Solution Approach 1:
The patent employs dynamically controllable inverter structures whose inversion behavior can be switched on or off based on operational needs. By using control signals applied to the controllable inverters, the system can dynamically adjust whether correction is active, minimizing timing delays when correction is not needed while maintaining reliability when errors occur
Solution Approach 2:
The patent changes the operational parameters of the inverter structures by applying different control voltages or logic levels to enable/disable the inversion function. This parameter control allows the system to switch between correction mode and normal operation mode, reducing timing delays during normal operation while maintaining the ability to correct errors when needed
3Reliability
If additional inverters or buffers are added to correct logic inversion, then logic inversion errors are corrected, but surface area occupation increases
Solution Approach 1:
The patent designs multi-functional controllable inverter structures that can serve both as logic correction elements and as functional logic gates depending on their configuration. By sharing the same physical structures for multiple purposes, the patent reduces the additional surface area that would be required if separate dedicated correction inverters were added for each logic gate
Solution Approach 2:
The patent merges the correction inverter structures with the existing logic gate structures by integrating control mechanisms into the same physical footprint. This merging allows the correction functionality to be embedded within the existing device architecture rather than requiring separate additional components, thereby minimizing surface area occupation
Data Source
AI summary
Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.