Configurable Logic Cell Multiplication via Merged Adder and Multiplexer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Programmable Logic Devices (PLDs) lack efficient and fast multiplication capabilities, as their configurable logic cells are not designed for multiplication, requiring excessive hardware and introducing overheads, particularly due to the need for both AND gates and full adders in each multiplier cell.
Innovation Solution
An integrated circuit with a configurable logic cell that implements multiplication by integrating a full adder and partial product generator within a single cell, replacing the AND gate with a multiplexer to reduce hardware overhead, utilizing multiplexing means to manage inputs and outputs efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional AND gate and full adder configuration is used in each multiplier cell, then multiplication function is achieved, but hardware overhead and device complexity increase
Solution Approach 1:
The patent merges the AND gate and full adder into a single integrated logic cell structure. The configurable logic cell combines the partial product generation (traditionally AND gate) and addition (traditionally full adder) functions into one unified cell, reducing the number of discrete components and interconnections required for multiplication operations.
Solution Approach 2:
The configurable logic cell is designed to perform multiple functions including multiplication, addition, and other logical operations. By making the logic cell universal and reconfigurable, the same hardware structure can serve different purposes, eliminating the need for dedicated AND gates and full adders specifically for multiplication, thus reducing overall hardware overhead.
2Productivity
If separate AND gates and full adders are used in multiplier cells, then multiplication operation is performed, but circuit delays increase
Solution Approach 1:
By merging the AND gate and full adder into a single integrated cell, the patent eliminates the propagation delay associated with signals traveling between separate AND gate outputs and full adder inputs. The integrated structure allows simultaneous computation of partial products and their summation within the same logic cell, reducing overall circuit delay.
3Adaptability or versatility
If traditional PLD architecture is used without dedicated multiplication cells, then PLD versatility is maintained, but multiplication efficiency is poor
Solution Approach 1:
The configurable logic cell maintains the PLD's versatility by being reprogrammable for different logical functions while simultaneously optimizing for multiplication operations. The cell can be configured through programming to perform multiplication efficiently while retaining the ability to perform other logical operations, thus maintaining PLD universality without sacrificing multiplication efficiency.
Data Source
AI summary
The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.