Logic Cell-Based PUF Generator Circuit Design
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Solution Overview
Problem
SRAM-based PUF generators are inefficient due to layout design rules requiring extra distance to isolate SRAM arrays from other logic transistors, necessitating a more compact and efficient design.
Innovation Solution
A PUF generator based on logic transistors using a PUF cell array with bit cells configured in a column-row layout, employing 12-T or 7-T SRAM bit cells and cross-coupled inverters to generate unique and stable logical states without the need for a sense amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF generator uses layout design rules to isolate SRAM arrays from other logic transistors, then reliability is improved, but area increases and manufacturing efficiency deteriorates
Solution Approach 1:
The patent merges SRAM array functionality with logic transistor functionality into a unified structure where logic transistors serve dual purposes as both computational elements and PUF elements. This integration eliminates the need for separate isolation zones, reducing total area while maintaining reliability through the inherent stability of logic-based metastable states.
Solution Approach 2:
The logic transistors in the PUF generator perform multiple functions: they act as both the computational logic elements and the PUF storage elements. This multi-functionality eliminates the need for dedicated isolation structures, as the same transistor array serves both purposes, thereby reducing area overhead while maintaining reliability.
2Reliability
If SRAM-based PUF generator follows layout design rules for isolation, then reliability is improved, but manufacturing efficiency deteriorates
Solution Approach 1:
The patent combines SRAM array and logic transistor functions into a single integrated structure, eliminating the need for complex isolation layout rules. This simplification streamlines the manufacturing process, reduces design complexity, and improves manufacturing efficiency while maintaining the reliability needed for secure PUF operation.
Solution Approach 2:
The patent changes the fundamental operating parameters from SRAM-based stable states to logic-based metastable states. This parameter change allows the use of standard logic transistor fabrication processes without requiring specialized SRAM isolation techniques, thereby improving manufacturing efficiency and yield while maintaining reliability through the inherent stability of logic circuit metastable states.
3Area of stationary object
If logic cell-based PUF generator eliminates sense amplifier, then area and cost are reduced, but measurement precision may deteriorate
Solution Approach 1:
The patent extracts and removes the sense amplifier component from the traditional SRAM-based PUF architecture. By eliminating this external component, the design achieves area reduction and cost savings while maintaining measurement precision through the use of logic circuit internal states that naturally provide sufficient signal strength for direct readout.
Solution Approach 2:
The logic-based PUF cell structure provides self-sufficient output signaling capability, where the metastable state of the logic circuit directly produces detectable output signals without requiring external sense amplification. This self-service capability maintains measurement precision while eliminating the need for additional sense amplifier circuits, thereby reducing area and cost.
Data Source
AI summary
Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.