Programmable Logic Cell Multiplexing for Routing and Power Savings
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Solution Overview
Problem
Existing programmable logic device architectures inefficiently use routing resources and consume excessive power due to the need for additional resources and dynamic selection mechanisms.
Innovation Solution
The implementation of a logic cell with multiple multiplexors and a register that allows for flexible selection between combinatorial and sequential functions using minimal routing resources, along with a gated clock signal to reduce power consumption when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional logic cell architecture with separate multiplexors and registers is used, then routing flexibility is maintained, but routing resources are inefficiently used and power consumption increases
Solution Approach 1:
The patent combines the select signal input and data input into a single shared routing resource. The first input terminal receives a select signal that is dynamically reused as a data input to the second multiplexor, eliminating the need for separate dedicated routing paths for select and data signals. This merging reduces routing resource usage while maintaining full functional flexibility of the logic cell.
Solution Approach 2:
The first input terminal serves multiple functions: it receives select signals for the first multiplexor during combinatorial logic operations, and serves as a data input for the second multiplexor during sequential operations. This multi-functional input terminal reduces the total number of routing resources required while maintaining adaptability for both combinatorial and sequential logic functions.
2Adaptability or versatility
If additional resources and dynamic selection mechanisms are added to logic cells, then functional flexibility is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the select signal path and data input path by having the first input terminal serve dual purposes. This reduces the total number of separate routing resources and control signals needed, thereby reducing device complexity while maintaining the ability to implement both combinatorial and sequential logic functions with full flexibility.
Solution Approach 2:
The first input terminal is designed as a universal interface that can accept either a select signal or a data input depending on the operational mode. This multi-functionality eliminates the need for additional dedicated inputs and control mechanisms, reducing overall device complexity while preserving functional versatility.
3Reliability
If clock signal is continuously provided to register, then sequential operation reliability is maintained, but dynamic power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating where the clock signal to the register is enabled only when the third multiplexor selects the register output as the logic cell output. When combinatorial logic output is selected, the clock is gated off. This dynamic control maintains sequential operation reliability when needed while eliminating unnecessary power consumption during combinatorial operations.
Solution Approach 2:
The clock signal to the register is provided periodically rather than continuously, synchronized with the selection signal of the third multiplexor. The clock is activated only during time periods when sequential output is required, reducing dynamic power consumption while ensuring reliable sequential operation when the logic cell is configured for sequential functions.
Data Source
AI summary
A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.