Timing Analysis for Complex Logic Cells with Distorted Waveforms
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Solution Overview
Problem
Current timing analysis methods, such as timing arc based models and channel connected block (CCB) based current models, are inadequate for complex logic cells in coupled networks due to limitations in handling distorted waveforms and distributed parasitic capacitances, leading to inaccurate results and inability to model complex circuits effectively.
Innovation Solution
A method combining timing arc based models with CCB based current models to perform timing analysis by dividing logic cells into initial, middle, and final circuits, generating intermediary signals to compute output signals, and using equivalent input signals to approximate coupled network effects, thereby improving accuracy for complex logic cells with distorted input waveforms and coupled load networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing arc based models are used for timing analysis, then timing accuracy for isolated logic cells is improved, but accuracy deteriorates when logic cells are embedded in coupled networks with distorted waveforms
Solution Approach 1:
The logic cell is divided into multiple channel connected blocks (CCBs), where each CCB is modeled separately using current-based models. This segmentation allows the timing analysis to account for distorted waveforms and coupled network effects by analyzing each block's contribution to the overall timing behavior, thereby maintaining accuracy in complex coupled network scenarios.
Solution Approach 2:
The invention transitions from using fixed timing arc parameters to dynamically computing timing parameters based on actual waveform characteristics and coupled network conditions. By adjusting timing parameters according to the specific distorted waveform and coupled network configuration, the model maintains high accuracy across diverse scenarios while adapting to coupled network environments.
2Measurement precision
If channel connected block based current models are used for coupled network analysis, then accuracy for distorted waveforms is improved, but device complexity increases
Solution Approach 1:
By dividing the logic cell into discrete channel connected blocks, each with its own current model, the invention enables modular analysis of complex circuits. This segmentation allows accurate modeling of distorted waveforms and coupled networks while maintaining manageable complexity through systematic decomposition of the overall timing analysis into block-level computations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate timing analysis for complex logic cells in coupled networks by generating equivalent input signals and output signals, effectively addressing the limitations of existing methods and providing precise timing characteristics for integrated circuits.
Implementation Method 1
parasitic capacitances cause a capacitive coupling between signal nets 123 and 121 as represented by parasitic capacitor 124
Implementation Method 2
The parasitic coupling of the signal nets in coupled network 120 may cause cross talk and other noise issues for final output signal F_OUT_S of logic cell 110
Data Source
AI summary
A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.