Compact Logic Cells With Backside Routing for Lower Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit cell designs face challenges with increased routing complexity and parasitic resistance/capacitance due to smaller component sizes, limiting performance and increasing manufacturing costs.
Innovation Solution
The implementation of compact logic cells with full backside connectivity, utilizing gate-all-around field effect transistors and additional backside interconnects, allows for both frontside and backside routing, reducing cell size and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If component sizes are miniaturized to advance computing power, then integration density is improved, but routing complexity and parasitic resistance/capacitance increase
Solution Approach 1:
The patent introduces backside connectivity as a new dimension for routing, transitioning from traditional planar frontside-only interconnects to three-dimensional routing that utilizes both frontside and backside of the substrate. This allows signals to be routed from the backside contact layers (BM0, BM1) through the substrate to frontside components, effectively adding a vertical dimension to the routing topology and reducing planar routing complexity.
Solution Approach 2:
The patent segments the interconnect system into separate frontside and backside contact layers (FS-ILD/BS-ILD) with independent metal layers (FM0/BM0, FM1/BM1). This segmentation allows routing functions to be distributed across different layers and sides of the substrate, reducing the complexity burden on any single layer and enabling more efficient signal paths.
2Area of moving object
If component sizes are miniaturized, then integration density is improved, but parasitic resistance and capacitance increase
Solution Approach 1:
By implementing backside connectivity with dedicated backside contact layers and metal interconnect layers, the patent creates shorter and more direct signal paths. Signals can be contacted from the backside of the substrate and routed through lower-parasitic backside layers before reaching active components, reducing the total parasitic resistance and capacitance compared to traditional frontside-only routing that requires longer lateral paths.
Solution Approach 2:
The backside substrate acts as an intermediary medium for signal transmission. Instead of routing all signals through the frontside interconnect layers, the patent uses the backside contact layers (BM0, BM1) as intermediary routing paths that can directly contact components from below, reducing the parasitic burden on frontside interconnects.
3Ease of manufacture
If frontside-only routing is used, then manufacturing is simpler, but internal routing resources are insufficient
Solution Approach 1:
The patent segments the routing resources into frontside-specific and backside-specific interconnect systems. Each side has its own contact layers (FS-ILD, BS-ILD) and metal layers (FM0/BM0, FM1/BM1), allowing independent optimization and utilization of routing resources on each side without interfering with manufacturing processes.
Solution Approach 2:
The substrate serves multiple functions: it acts as both the mechanical support structure and as an active routing medium through backside connectivity. The backside contact layers and metal layers provide additional routing functionality while maintaining compatibility with standard frontside manufacturing processes, achieving multi-functionality without sacrificing manufacturing simplicity.
Data Source
AI summary
Compact logic cells using full backside connectivity are disclosed. In an aspect, a semiconductor device comprises a plurality of integrated circuit cells comprising: gates separated by source/drain (S/D) structures and comprising at least one channel extending through a metal structure and connecting adjacent S/D structures to each other, at least one gate forming a gate-all-around field effect transistor; an FS contact electrically connecting to an S/D structure; an FS contact electrically connecting to a gate; a frontside (FS) inter-layer dielectric (ILD) on the gates and S/D structures; FS metal zero interconnects disposed on the FS-ILD, one being electrically connected to an FS contact; a BS contact electrically connecting to an S/D structure; a BS contact electrically connecting to a gate; a backside (BS) ILD disposed on the gates and S/D structures; and BS metal zero interconnects disposed on the BS-ILD, one being electrically connected to a BS contact.