Configurable Logic Cells for Synchronized Output Sampling
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Solution Overview
Problem
Existing logic devices with single-pin configurations for inputs and outputs lead to asynchronous sampling of configurable logic cells, resulting in misleading results due to independent instantiation and limited application versatility, and prior art does not provide a minimal circuit implementation solution.
Innovation Solution
An integrated circuit with a central processing core and multiple peripherals, including configurable logic cells with enhanced input/output connections, allowing for real-time software configuration and cascading of cells, enabling simultaneous reading of outputs and complex logic function implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configurable logic cells are instantiated independently with single-pin I/O configurations, then each cell can be configured independently, but the outputs cannot be sampled simultaneously leading to misleading results
Solution Approach 1:
The patent merges multiple individual cell output registers into a single unified output register that can be read simultaneously. The configurable logic cells are combined with a shared output register that captures all cell outputs at the same clock edge, allowing simultaneous sampling of all cell outputs through a single read operation.
Solution Approach 2:
The patent introduces an intermediary output register that acts as a buffer between the configurable logic cells and the CPU. This intermediary structure collects outputs from multiple independently instantiated cells and presents them in a synchronized manner, resolving the timing inconsistency without changing the independent cell configuration.
2Device complexity
If a single logic device package is used with one pin per I/O, then the device structure is simple, but the number of pins required increases with more logic inputs and outputs
Solution Approach 1:
The patent implements multi-functionality by allowing configurable logic cells to have multiple input sources including external pins and internal signals from other cells or subsystems. This universal input capability means fewer external pins are needed since internal routing can provide additional inputs without requiring additional package pins.
Solution Approach 2:
The patent adds an internal routing dimension to the I/O architecture. Instead of relying solely on external package pins, the system creates a multi-dimensional input structure where signals can originate from external pins, internal subsystems, or other logic cells, effectively increasing the input capacity without increasing the pin count.
3Device complexity
If configurable logic cells have only a single logic function and state variable, then the circuit implementation is minimal, but the application versatility is limited
Solution Approach 1:
The patent introduces dynamic reconfigurability to the logic cells. Each cell can be programmed at runtime to implement different logic functions (AND, OR, XOR, NAND, NOR, XNOR) and can operate in different modes (combinatorial logic, state machine, or I/O peripheral). This dynamic capability allows a single minimal circuit structure to serve multiple applications.
Solution Approach 2:
The patent enables parameter changes by allowing the logic function and operational mode of each cell to be modified through software configuration. The cells can change their behavior parameters (logic function type, input/output assignment, state variable configuration) without changing their physical structure, achieving versatility through parameter reconfiguration.
4Ease of operation
If the CPU performs multiple read operations to determine the state of each cell bit, then each cell can be independently addressed, but the read operations are time-consuming and asynchronous
Solution Approach 1:
The patent combines multiple individual read operations into a single unified read operation. By merging the outputs of multiple configurable logic cells into a single output register, the system allows the CPU to read all cell states simultaneously in one operation, eliminating the time required for multiple sequential reads.
Solution Approach 2:
The patent performs preliminary action by pre-collecting all cell outputs into a unified register before the CPU read operation. The output register is prepared and loaded with all cell states at the appropriate clock cycle, so when the CPU performs the read operation, all data is already available simultaneously, eliminating waiting time.
Data Source
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AI summary
An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.