Configurable Logic Cells With Real-Time Software Reconfiguration
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Solution Overview
Problem
Conventional Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) require additional resources and static configuration, which does not lead to a minimal circuit implementation, and lack real-time software access and dynamic configuration capabilities.
Innovation Solution
A processor with a RISC CPU core and configurable logic cell peripherals that allow real-time software access and configuration, operating independently of the processor, using D-latch or JK flip-flop technology, and configurable via software registers or non-volatile memory, enabling dynamic logic function implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FPGA and PLD logic cells use D flip-flop technology for configurable logic, then the device can provide configurable logic cells for general purpose use, but the circuit implementation is not minimal and uses more resources than necessary
Solution Approach 1:
The patent changes the fundamental parameter of the storage element from D flip-flop to JK flip-flop technology. The JK flip-flop provides configurable logic functionality with fewer resources by utilizing its ability to perform multiple logic operations (AND, OR, NAND, NOR, XOR, XNOR) through different J and K input combinations, thereby achieving minimal circuit implementation while maintaining adaptability
Solution Approach 2:
The JK flip-flop based logic cell is designed to perform multiple logic functions (AND, OR, NAND, NOR, XOR, XNOR) within a single unified structure. This multi-functionality eliminates the need for separate dedicated circuits for each logic operation, reducing overall device complexity while preserving full configurability
2Ease of manufacture
If conventional FPGA and PLD logic cells use static configuration, then the configuration is simple to implement, but the logic cannot be reconfigured in real-time and lacks dynamic adaptability
Solution Approach 1:
The patent introduces dynamic reconfiguration capability by allowing the J and K inputs of the flip-flop to be controlled by software registers. This enables the logic cell to be reconfigured in real-time during operation, transitioning from a static to a dynamic system that can adapt its logic function based on runtime requirements while maintaining ease of configuration through software control
3Device complexity
If conventional FPGA and PLD logic cells lack software access to internal configuration, then the device structure is simpler, but the logic cannot be controlled or inspected by software in real-time
Solution Approach 1:
The patent introduces software-accessible registers as an intermediary between the external software environment and the internal JK flip-flop configuration. These registers serve as a control interface that allows software to write configuration values to the J and K inputs, enabling full software control and inspection of the logic cell while adding minimal structural complexity
4Loss of energy
If the processor is halted to reduce power consumption or allow inspection, then power consumption is reduced, but productivity and operational continuity are affected
Solution Approach 1:
The patent segments the system into an independent logic cell peripheral that can operate autonomously from the main processor. This segmentation allows the logic cell to continue functioning during processor sleep or halt modes, maintaining operational continuity for critical functions while the processor conserves power, thus resolving the contradiction between energy savings and productivity
Data Source
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AI summary
A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.