Multi-chip Package Logic Chip Substrate Opening
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Solution Overview
Problem
Existing multi-chip packages face challenges in reducing width and thickness while maintaining effective electrical connections, often resulting in voids due to insufficient molding material in narrow spaces and increased thickness from thick die attach films.
Innovation Solution
A multi-chip package design featuring a package substrate with an opening, a connecting substrate, and stacked semiconductor chips, where the logic chip is positioned within the opening and electrically connected through the connecting substrate, minimizing width and thickness by using a thin connecting substrate and underfilling layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the logic chip is arranged closely to the lowermost semiconductor chip to decrease package width, then the package width is reduced, but voids are generated in the molding member due to insufficient molding material supply
Solution Approach 1:
The logic chip is positioned in the opening of the package substrate, utilizing the vertical dimension and central space rather than lateral arrangement. This dimensional repositioning allows the logic chip to be integrated without increasing package width while ensuring adequate molding material supply from all directions, preventing void formation.
Solution Approach 2:
The logic chip is nested within the opening of the package substrate, with the connecting substrate positioned between the logic chip and semiconductor chips. This nested configuration optimizes space utilization, reduces package width, and ensures proper molding material distribution throughout the structure.
2Length of stationary object
If a thick die attach film is used to arrange the logic chip, then the logic chip can be positioned to decrease package width, but the package thickness increases
Solution Approach 1:
A thin connecting substrate is used instead of a thick die attach film to electrically connect the logic chip to the semiconductor chips. This thin film approach maintains the logic chip's positioned arrangement for reduced package width while minimizing the increase in package thickness.
Solution Approach 2:
The logic chip is positioned in the opening of the package substrate, utilizing vertical and central space. This dimensional repositioning eliminates the need for thick die attach films, thereby reducing package thickness while maintaining the width-reduction benefit.
3Reliability
If bond fingers are formed on the upper surface of the package substrate outside the logic chip, then electrical connections are established, but the package width increases
Solution Approach 1:
The connecting substrate integrates multiple functions: it provides electrical connection between the logic chip and semiconductor chips, supports the logic chip within the opening, and enables signal routing. This merging of functions eliminates the need for separate bond fingers extending outside the logic chip, thereby reducing package width while maintaining electrical connectivity.
Solution Approach 2:
Electrical connections are established through the connecting substrate positioned vertically between the logic chip and semiconductor chips, rather than through lateral bond fingers. This vertical connection approach reduces the lateral footprint and package width while ensuring reliable electrical connectivity.
Data Source
AI summary
A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.