Automated Test Pattern Generation for Logic Circuits Using SAT Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing automated test pattern generation (ATPG) tools are unable to detect all stuck-at faults in digital circuits, particularly for large circuits, and fail to identify redundant faults, leading to incomplete test coverage.
Innovation Solution
A computing device with a logic preprocessor, lock circuit generator, and fault analyzer is used to identify stuck-at faults, generate locked logic circuits, and perform Boolean satisfiability attacks to determine if input test patterns exist for each fault, thereby identifying redundant faults and achieving 100% coverage of non-redundant faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing ATPG tools are used for test pattern generation, then the testing process is automated and efficient, but the test coverage is incomplete as not all stuck-at faults can be detected
Solution Approach 1:
The patent segments the test generation process into multiple specialized modules: a logic preprocessor for circuit analysis, a lock circuit generator for creating locked versions, and a fault analyzer for SAT-based analysis. This segmentation allows each module to specialize in specific tasks, achieving both efficiency and complete fault coverage that monolithic ATPG tools cannot achieve
Solution Approach 2:
The patent introduces locked logic circuits as an intermediary between the original circuit and the test pattern generation process. By inserting key gates to create locked versions of the circuit, the system enables SAT-based analysis to indirectly detect faults that direct ATPG methods miss, thereby improving coverage while maintaining automation
2Reliability
If comprehensive test patterns are generated to detect all faults, then fault detection coverage improves, but the testing time increases
Solution Approach 1:
The logic preprocessor performs preliminary analysis of the circuit structure, identifying fanout segments and potential stuck-at faults before the main test generation process. This preliminary action prepares the circuit representation in advance, enabling faster SAT-based analysis and reducing overall testing time while maintaining complete coverage
Solution Approach 2:
The patent creates locked copies of the original logic circuit with inserted key gates. These copied structures enable parallel analysis of multiple fault scenarios through SAT solving, allowing comprehensive fault detection without sequentially testing each fault individually, thus reducing testing time
3Reliability
If locked logic circuits with key gates are inserted to enable SAT-based analysis, then redundant faults can be identified, but the device complexity increases
Solution Approach 1:
The patent extracts only the necessary portions of the circuit for SAT-based analysis by selectively inserting key gates at specific locations identified by the logic preprocessor. Rather than locking the entire circuit, this extraction approach focuses computational resources on critical segments, enabling redundant fault identification with minimal added complexity
Solution Approach 2:
The lock circuit generator applies different processing to different parts of the circuit based on local characteristics. Key gates are inserted only where needed to create testable locked versions, and the SAT analyzer focuses on local satisfiability conditions at specific fault locations, rather than analyzing the entire circuit uniformly, thus managing complexity
Data Source
AI summary
Technologies for automated test pattern generation include a computing device that identifies one or more stuck-at faults in a logic circuit. The computing device inserts a key gate in the logic circuit at a stuck-at fault to generate a locked logic circuit. The computing device performs a Boolean satisfiability attack to determine an input test pattern associated with the fault and, if no input test pattern exists, identify the fault as redundant. The computing device may identify multiple undetected faults in the logic circuit. The computing device may generate and analyze a separate locked circuit for each undetected fault and/or generate and analyze a locked circuit that models all of the undetected faults. The computing device may test a device under test with all of the generated input test patterns associated with the undetected faults. Other embodiments are described and claimed.