Logic Circuit Layout With Data-Dependent Delays Against Power Analysis
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Solution Overview
Problem
Existing logic circuits are vulnerable to power analysis attacks due to their predictable power consumption patterns, which can be exploited by attackers to reveal secret information, despite the use of countermeasures like dual-rail logic and random delay insertion.
Innovation Solution
The introduction of data-dependent delays into the circuit layout, where delays are strategically inserted along logic paths to create intra-cycle variations, making it difficult for attackers to correlate current consumption with specific data transitions, thereby increasing randomness and reducing vulnerability to power analysis attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If countermeasures like dual-rail logic and random delay insertion are used to protect against power analysis attacks, then security against power analysis attacks is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making the delay values data-dependent rather than fixed or purely random. The delay elements dynamically adjust their delay characteristics based on the actual data being processed, creating a dynamic protection mechanism that adapts to different operational states while maintaining security against power analysis attacks
Solution Approach 2:
The patent changes the parameter of delay time from being constant or randomly fixed to being data-dependent. By varying the delay parameter based on input data characteristics, the circuit creates unpredictable power consumption patterns that prevent attackers from correlating power measurements with specific data values, thereby improving security without requiring complete circuit redesign
2Reliability
If data-dependent delays are inserted along logic paths to create intra-cycle variations, then immunity to power analysis attacks is improved, but device complexity increases
Solution Approach 1:
The patent introduces delay elements as intermediary components inserted along the logic paths. These delay elements act as mediators that modify the timing characteristics of signal propagation without fundamentally changing the logic functionality. By placing these intermediaries strategically, the circuit achieves data-dependent timing variations that disrupt power analysis attacks while maintaining the original circuit's logical behavior
Solution Approach 2:
The patent segments the logic paths by inserting discrete delay elements at specific locations along the signal propagation paths. This segmentation allows independent control of delay characteristics in different parts of the circuit, enabling precise manipulation of intra-cycle timing variations to maximize security effectiveness while minimizing overall complexity
3Reliability
If delay elements are added to create data-dependent noise, then signal-to-noise ratio for attackers is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-service by using the circuit's own operational characteristics (data values being processed) to automatically control the delay elements. The delay elements respond to the actual data flowing through the circuit, creating noise patterns that are inherently tied to the computation being performed. This self-regulating mechanism reduces the need for external control and minimizes manufacturing precision requirements since the system adapts to its own operational state
Data Source
AI summary
A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes:obtaining an initial circuit design;specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; andforming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.