Logic Circuit Emulating Safety Relay Contacts
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Solution Overview
Problem
Existing solutions fail to accurately and timely replicate the behavior of safety relays in relay interlockings, leading to potential failures and route blockages when transitioning from traditional relay systems to programmable logic components, such as FPGA-based systems, due to the specific temporal and safety-related characteristics of safety relays.
Innovation Solution
A logic circuit with two channels that mimics the behavior of safety relays by simulating the opening and closing of contacts, using transistors to manage signal voltages based on input changes and delay times, ensuring correct emulation of safety relay behavior in programmable logic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional relay interlockings are replaced with programmable logic components (FPGA), then modernization and long-term maintainability are improved, but the specific temporal behavior and safety characteristics of safety relays are not accurately replicated, leading to potential failures and route blockages
Solution Approach 1:
The patent creates a logical copy of the safety relay's behavior within the FPGA by implementing equivalent logic circuits that replicate the relay's contact switching characteristics, timing behavior, and safety functions. This copying approach allows the FPGA to emulate the relay's temporal and safety characteristics while providing modern programmability and maintainability.
2Device complexity
If safety relays are replaced with simple programmable logic, then device complexity is reduced, but the specific temporal behavior (opening/closing timing) of safety relay contacts is not accurately maintained, causing potential safety failures
Solution Approach 1:
The patent implements preliminary timing mechanisms within the FPGA logic that pre-establish the correct temporal sequence for contact opening and closing operations. By building the timing behavior into the logic circuit design itself, the system ensures that contacts switch at the correct moments without requiring complex external timing circuits or manual synchronization.
3Productivity
If relay interlockings are completely replaced with electronic interlockings, then productivity and maintenance ease are improved, but the specific safety characteristics (normally closed contact behavior, potential free contacts) are lost, leading to route blockages
Solution Approach 1:
The patent designs the FPGA logic to universally handle multiple safety relay functions including normally closed contact emulation, potential free contact generation, and various timing sequences. The single programmable device can perform multiple safety functions that traditionally required different hardware configurations, providing both maintenance ease and safety characteristic preservation.
Data Source
Figure 1
AI summary
According to the invention, a logic circuit (2) and a method for replacing a positively driven safety relay (4), which has a signal circuit contact (R), a normally closed contact (A) with a normally closed input (In_A) and a normally closed output (Out_A), and a normally open contact (B) with a normally open input (In_B) and a normally open output (Out_B), are disclosed, wherein the logic circuit (2) is equipped with two channels, comprising a first logic channel (K1) and a second logic channel (K2); comprising: a) for each logic channel (K1, K2) a first input (Set1, Set2) which, upon a voltage change, simulates a closing or opening of the signal circuit contact (R) and accordingly assumes a value from LOW to HIGH or HIGH to LOW;b) for each logic channel (K1, K2) a first output (OuO1, OuO2) which is set to LOW by a voltage change at the first input (Set1, Set2) and sets a second input (COu01, COu02) to LOW on the other logic channel (K1, K2), whereby the setting of the second input (COu01, COu02) to LOW in the respective logic channel is checked before a first test signal (Test01, Test02) is applied to the normally closed input (In_A); c) for each logic channel (K1, K2) a third input (In_01, In_02) which, upon a voltage change triggered by the first test signal (Test01, Test02), simulates the opening of the normally closed contact (A) and triggers a further check in the respective logic channel (K1, K2) to see if the first output (OuO1, Ou02) is LOW, before a predetermined delay time elapses by means of a delay logic;d) for each logic channel (K1, K2) a fourth input (InC1, InC2) coupled to the normally open input (In_B), which simulates the closing of the normally open contact (B) upon a voltage change, thereby setting a second output (OuC1, OuC2) to HIGH; and wherein e) two transistors (T1, T2) connected in series do not pass a signal voltage (V+) to the normally closed output (Out_A) if at least one of the first two outputs (Ou01, Ou02) is LOW; and wherein f) two further transistors (T3, T4) connected in series pass the signal voltage (V+) to the normally open output (Out_B) if both second outputs (OuC1, OuC2) are HIGH.