Configurable Logic Circuit Fault Detection via Signal-Linked Memory Segmentation
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Solution Overview
Problem
Conventional methods for checking hardware-configurable logic circuits for faults are time-consuming, often taking over 10 ms, which exceeds the fault tolerant time required for safety-critical applications like the automotive industry, necessitating a quicker and more reliable fault detection method.
Innovation Solution
The method focuses on checking only the subareas of the configuration memory involved in generating the output signal, using a data flow-oriented approach with error correcting codes and prioritization to ensure rapid fault detection and minimize fault detection time, adhering to safety standards like ISO 26262.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all subareas of the configuration memory are checked for faults, then the reliability of fault detection is improved, but the fault detection time increases to 10 ms or more
Solution Approach 1:
The configuration memory is divided into multiple subareas, each associated with specific circuit areas. Instead of checking all subareas uniformly, the invention segments the checking process to only examine subareas that are actually involved in generating the current output signal. This segmentation allows the system to maintain comprehensive fault detection coverage for relevant areas while eliminating unnecessary checks of unrelated subareas, thereby reducing overall fault detection time while preserving reliability for critical paths.
Solution Approach 2:
The invention applies partial action by checking only the necessary subset of configuration memory subareas rather than performing a complete check of all subareas. By identifying and checking only those subareas that are involved in the current output signal generation, the system performs sufficient fault detection for safety-critical paths without the excessive time cost of a full memory check, achieving an optimal balance between reliability and speed.
2Loss of time
If the fault detection time is reduced to meet fault tolerant time requirements, then the safety-critical requirements are satisfied, but the checking method becomes more complex
Solution Approach 1:
The invention implements preliminary action by pre-establishing associations between output signals and the configuration memory subareas that generate them. This is achieved through address lists that are created in advance during system initialization or design phase. When a fault check is needed, the system simply retrieves the pre-computed address list corresponding to the current output signal, eliminating the need for complex real-time analysis of which subareas to check. This preliminary preparation significantly reduces fault detection time while keeping the runtime checking logic simple.
Solution Approach 2:
The invention introduces address lists as an intermediary data structure that mediates between the complex configuration memory organization and the simple fault checking operation. These address lists serve as a lookup table that directly maps output signals to their corresponding configuration subareas. This intermediary layer abstracts the complexity of determining which subareas to check, allowing the fault detection mechanism to operate simply by following pre-computed addresses, thereby reducing both time and operational complexity.
Data Source
AI summary
A method is described for checking a hardware-configurable logic circuit including circuit areas and including a configuration memory having different subareas for faults, a respective configuration of hardware elements of one of the circuit areas being defined by configuration data stored in an associated subarea of the configuration memory, and when at least one checking requirement in regard to an output signal which is provided by the hardware-configurable logic circuit is met, a fault check of the configuration data being carried out only in those subareas of the configuration memory of the hardware-configurable logic circuit which are involved in generating the output signal.