Logic Circuit Fault Location Estimation for Multiple Faults

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Solution Overview

Problem

Conventional fault location estimation systems for logic circuits face challenges such as long processing times for large-scale circuits, reduced accuracy due to neglecting error propagating paths, inability to handle multiple faults effectively, and difficulty in prioritizing physical analysis from output results.

Innovation Solution

The system classifies fault candidates into groups based on error-observation nodes, calculates combinations considering inclusion relations, and performs multiple-fault simulation to accurately estimate fault locations, reducing diagnostic time and improving accuracy by accounting for interacting error paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional fault location estimation systems use fan-in cone classification and single-fault simulation for each internal node, then fault location can be estimated, but processing time becomes excessively long for large-scale circuits

Engineering Contradiction:
Improvefault location estimation accuracyVSAvoiddiagnostic time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the fault diagnosis process into two distinct phases: (1) single-fault simulation phase where each internal node is simulated independently to generate fault candidates and error propagating paths, and (2) multiple-fault combination phase where pre-computed fault candidate groups are combined based on error-observation node relationships. This segmentation allows the computationally intensive single-fault simulations to be performed once and reused, avoiding redundant calculations in the multiple-fault analysis phase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary single-fault simulations for all internal nodes before the actual multiple-fault diagnosis. During this preliminary phase, fault candidates and error propagating paths are pre-computed and stored. In the subsequent multiple-fault analysis phase, these pre-computed results are reused to generate fault candidate groups and determine combinations, eliminating the need to re-simulate single-fault conditions and significantly reducing overall processing time.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If conventional systems neglect error propagating paths in fault simulation, then processing is simplified, but accuracy of fault location estimation deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidfault location estimation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary error propagating path analysis during the single-fault simulation phase, tracing how errors propagate from each internal node to error-observation nodes. These pre-computed error propagating paths are stored and reused in the multiple-fault combination phase to determine which fault candidates should be grouped together, ensuring accurate fault location estimation without requiring complex real-time path analysis.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If conventional systems perform single-fault simulation for each internal node without grouping, then fault candidates can be identified, but the ability to handle multiple faults effectively is reduced

Engineering Contradiction:
Improvefault candidate identificationVSAvoidmultiple fault handling capability
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent merges multiple single-fault simulation results by grouping fault candidates based on their error propagating paths to common error-observation nodes. Fault candidates that propagate errors to the same error-observation nodes are merged into a single fault candidate group. This merging process enables the system to handle multiple faults effectively by considering combinations of fault candidates within groups, thereby improving the system's adaptability to multiple fault conditions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal framework that handles both single-fault and multiple-fault conditions through the same error-observation node based grouping mechanism. The fault candidate groups and their combinations can explain various error output patterns, making the system universally applicable to different fault scenarios including single faults, multiple faults, and complex interacting fault conditions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Quantity of substance

If conventional systems output fault candidates without prioritization, then complete fault locations can be listed, but difficulty in prioritizing physical analysis increases

Engineering Contradiction:
Improvefault candidate list completenessVSAvoidphysical analysis prioritization
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

The patent applies local quality by differentiating fault candidate groups based on their specific error propagating paths and error-observation node relationships. Each fault candidate group is characterized by the specific error-observation nodes it affects and the error propagating paths it follows. This local differentiation enables prioritization of fault candidates based on their specific characteristics and impact, making physical analysis more efficient by focusing on the most likely fault locations first.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7844873B2Fault location estimation system, fault location estimation method, and fault location estimation program for multiple faults in logic circuit
Publication Date: 2010.11.30 RENESAS ELECTRONICS CORP
  • US7844873B2 patent drawing
  • US7844873B2 patent drawing
  • US7844873B2 patent drawing

AI summary

A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.