Logic Circuit Generation Device for Automated RTL Synthesis
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Solution Overview
Problem
High-level synthesis techniques face challenges in constructing and predicting the characteristics of high-performance logic circuits due to complex parallelism analysis and dependence on manual design, while SystemC methods struggle with design productivity and require extensive hardware description language usage.
Innovation Solution
A logic circuit generation device that converts a programming language description into a Register Transfer Level (RTL) description using a control flow graph, data flow graph, and logic circuit description, incorporating features like static single assignment form conversion and pipeline boundary arrangement to automate the synthesis process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If high-level synthesis technique is used to automatically convert software description to RTL description, then design time is reduced, but the construction of high-performance logic circuits becomes significantly complicated due to complex parallelism analysis and operation scheduling requirements
Solution Approach 1:
The patent segments the high-level synthesis process into distinct functional units: control flow graph generation, operation scheduling, binding, and FSMD generation. Each unit handles a specific aspect of the conversion, making the complex process more manageable and automatable without requiring manual intervention for parallelism analysis
Solution Approach 2:
The patent introduces intermediate data structures (control flow graph, operation schedule, binding information) that mediate between the software description and the final RTL output. These intermediaries facilitate automatic conversion by providing structured representations that can be processed algorithmically without manual analysis
2Reliability
If manual verification of state transition flow is performed in RTL design, then design quality can be maintained, but full verification fails and bugs are easily included in complicated data flow control scenarios
Solution Approach 1:
The patent implements feedback mechanisms where the generated FSMD is automatically verified against the original software description requirements. The control flow graph and operation scheduling steps provide feedback loops that ensure the synthesized RTL maintains equivalence with the source software, enabling complete verification even for complicated data flow controls
Solution Approach 2:
The high-level synthesis tool performs self-verification by automatically checking the generated FSMD against the input software description. This self-service capability eliminates the need for manual verification while ensuring design quality, as the tool itself verifies correctness through algorithmic comparison of control flows and data dependencies
3Adaptability or versatility
If SystemC with transaction level modeling is used to abstractly represent system functions, then system-level simulation is enabled, but design productivity remains limited and extensive hardware description language usage is still required
Solution Approach 1:
The patent creates a universal high-level synthesis framework that can process various software programming languages and convert them to RTL descriptions. This multi-functional approach enables system-level simulation while maintaining high productivity, as the same framework handles different programming paradigms without requiring extensive HDL knowledge from users
Solution Approach 2:
The patent replaces the mechanical process of manual HDL coding with an automated software-to-RTL conversion system. By substituting the manual writing of hardware description language with automatic synthesis from software descriptions, design productivity increases significantly while retaining system-level simulation capabilities through the generated RTL
Data Source
AI summary
A specific information processing function, which assumes circuit implementation, is described in a programming language, and from this description, an RTL description that can be logic synthesized is automatically generated. A logic circuit generation device includes: a control flow graph generation unit that generates a control flow graph; a control flow degenerate conversion unit that generates a control flow degenerate program by removing all condition branch instructions from the control flow graph; a data flow graph generation unit that generates a data flow graph from the control flow degenerate program; and a logic circuit description output unit that generates logic circuit description indicating a sequential circuit in which a rooted branch of the data flow graph corresponds to the wiring of the logic circuit and a node of the data flow graph corresponds to a computing element of the logic circuit.