Logic Circuit Hazard Check via CNF Conversion
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Solution Overview
Problem
Existing systems for generating logic circuits fail to account for glitches in exceptional timing paths, leading to hazards when these glitches are conveyed to flip-flops, causing defective circuit operations, and lack effective methods for detecting such hazards.
Innovation Solution
A hazard check method and device that convert the possibility of hazards into a satisfiability problem, utilizing a circuit conjunctive normal form (CNF) generating method to trace logic operations from a start point to an end point, setting boundary conditions for exceptional timing signals, and employing a satisfiability decision unit to check for hazards in logic circuits with synchronous and multi-cycle paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic circuit synthesis is performed without considering exceptional timing paths, then circuit generation speed is improved, but hazards occur when glitches are conveyed to flip-flops
Solution Approach 1:
The patent applies preliminary action by performing hazard checks during the logic synthesis phase before the circuit is implemented. The hazard check device analyzes exceptional timing paths and identifies potential hazards in advance, allowing designers to correct issues before circuit fabrication, thus maintaining both synthesis speed and reliability.
Solution Approach 2:
The patent introduces an intermediary hazard check device that acts as a mediator between the logic synthesis process and the final circuit implementation. This intermediary component analyzes the synthesized circuit for hazards without slowing down the main synthesis flow, resolving the contradiction between speed and reliability.
2Measurement precision
If hazard check methods using simulation with multiple signal states are used, then hazard detection capability is improved, but check time and complexity increase
Solution Approach 1:
The patent segments the hazard check process into distinct phases: identifying exceptional timing paths, analyzing glitch propagation, and determining hazard conditions. This segmentation allows the hazard check to focus only on relevant circuit portions rather than simulating the entire circuit with multiple signal states, reducing check time while maintaining detection capability.
Solution Approach 2:
The patent changes the analysis parameters by focusing on exceptional timing paths and their associated glitches rather than using comprehensive multi-state simulation. By parameterizing the hazard check around specific timing exceptions and glitch propagation paths, the method achieves high detection capability with reduced computational overhead.
Data Source
AI summary
A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion to only pre-embedded conjunctive normal form blocks if not all of the blocks in the logic circuit were embedded conjunctive normal form blocks; a means for tracing each termination point recorded in the signal information from the logic circuit, inputting the signal information to the circuit up to the flip-flop, and assigning numerals to each net; and a means for tracing each termination point recorded in the signal information from the logic circuit, referring to the logic library for each block, and searching for the same logic conjunctive normal form (CNF) as in the logic library, and substituting the conjunctive normal form into the numerals assigned to the connected network, and outputting it as the circuit conjunctive normal form; and a means for adding a circuit conjunctive normal form whose logic is equivalent to that numeral, to each net for each termination point recorded in the signal information.