Programmable Logic Circuit Timing for Shared Memory Conflict Avoidance
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Solution Overview
Problem
Simultaneous access to shared memory by multiple modules in programmable logic circuits often leads to delays due to memory conflicts, which existing technologies have not adequately addressed.
Innovation Solution
A programmable logic circuit design that delays the start of execution for a second module relative to a first module, ensuring that their memory access times do not overlap, by utilizing a delay time database to determine initial delay times and updating them based on measured waiting times to prevent conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple modules simultaneously access shared memory in programmable logic circuits, then parallel processing capability is improved, but memory access conflicts occur causing process delays
Solution Approach 1:
The patent applies preliminary action by calculating and setting delay times for module executions before actual memory access occurs. The delay time calculation unit computes the required delay in advance based on memory access patterns, and the delay unit applies this pre-calculated delay to prevent conflicts before they happen, thereby maintaining parallel processing efficiency while avoiding access conflicts.
2Reliability
If delay time is increased to avoid memory access conflicts, then memory access stability is improved, but execution speed of modules decreases
Solution Approach 1:
The patent implements dynamics by making delay times adjustable and adaptive rather than fixed. The delay time calculation unit dynamically computes optimal delay values based on actual memory access patterns and conflict situations. This allows the system to apply minimal necessary delays to prevent conflicts while maintaining high execution speed, rather than using excessive fixed delays that would slow down all operations.
3Loss of time
If delay time is calculated based on memory access patterns, then memory access conflicts are reduced, but system complexity increases
Solution Approach 1:
The patent applies feedback by using the actual memory access patterns and conflict detection results to continuously optimize delay time calculations. The system monitors memory access behavior and adjusts delay parameters based on observed patterns, creating a closed-loop control mechanism that reduces conflicts without requiring overly complex predetermined scheduling algorithms.
Data Source
AI summary
A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.