Logic Circuit Perturbation Detection via Programmable Datapath
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Solution Overview
Problem
Existing methods for preventing side-channel attacks in logic circuits are either costly, complex, or lead to material execution failures due to glitches, and cannot fully prevent signal leakage, making them inefficient in detecting perturbations such as glitches introduced by hackers.
Innovation Solution
A method and logic circuit with a test circuit that operates in two modes: calibration and detection, using a programmable length datapath to determine a critical propagation delay and detect perturbations, allowing for efficient detection of glitches while being fully digital and adaptable to variations in process, voltage, and temperature, thus minimizing the risk of material execution failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If noise is introduced to blind hackers to meaningful reverse analysis information, then side-channel attack resistance is improved, but material execution failures occur due to glitches
Solution Approach 1:
The patent applies preliminary action by performing calibration before detection mode operation. The test circuit first determines the critical propagation delay by varying the programmable length datapath and identifying when errors are generated, then uses this information to set up the detection mechanism. This preliminary calibration ensures that the detection circuit is properly configured before actual perturbation detection begins, preventing false positives while maintaining attack resistance.
Solution Approach 2:
The patent implements feedback through the error generator that continuously monitors the output of the test circuit and compares it against expected values. When the output differs from expected results, the error generator signals a perturbation condition. This feedback mechanism allows the system to detect side-channel attacks while automatically adjusting or alerting operators to potential material execution failures, thus resolving the contradiction between attack resistance and execution reliability.
2Difficulty of detecting and measuring
If detection circuits are designed to detect power supply glitch attacks, then perturbation detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a test circuit that serves multiple functions: it acts as both a calibration mechanism and a detection circuit. The same programmable length datapath is used to determine critical propagation delay during calibration and to detect perturbations during operation. The error generator serves dual purposes by identifying calibration boundaries and detecting attack conditions. This multi-functionality reduces overall device complexity while maintaining strong perturbation detection capability.
Solution Approach 2:
The patent implements dynamics through the programmable length datapath that can be dynamically adjusted during calibration to find the critical propagation delay point. The datapath length is varied to identify when errors are generated, allowing the system to adapt to different operating conditions. This dynamic adjustment capability enables the detection circuit to maintain optimal sensitivity without requiring overly complex fixed-structure circuits.
3Object-affected harmful factors
If timing modifications are introduced to blind hackers, then side-channel attack resistance is improved, but glitches are generated that are difficult to troubleshoot
Solution Approach 1:
The patent uses feedback through the error generator to monitor circuit output and compare it against expected values. When timing modifications cause glitches that lead to incorrect outputs, the error generator detects these deviations and generates error signals. This feedback mechanism makes glitch troubleshooting easier by automatically identifying when something has gone wrong, eliminating the need for complex manual debugging while maintaining attack resistance through the same feedback-based detection mechanism.
Data Source
AI summary
A method for detecting perturbations in a logic circuit including a plurality of datapaths coordinated by a clock signal and at least one test circuit having a programmable length datapath for varying a test propagation delay. The test circuit further including inputs, an output and an error generator for providing an error in case that the output is different than an expected output for the inputs. The test circuit having a calibration mode including determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error, adjusting the programmable length datapath to include therein a tolerance delay, and switching into a detection mode configured to detect a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error.