Logic Circuit Pulse Delay for Glitch-Free Signal Transitions
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Solution Overview
Problem
Electronic devices face challenges in performing logical operations without glitches due to overlapping logic level transition periods of input signals, which can lead to malfunctions.
Innovation Solution
The implementation of a pulse delay circuit and multiple logic circuits that generate input control pulses and output signals through synchronized operations, using inversion operators and exclusive OR gates to buffer and process input signals, ensuring that output signals are generated without glitches by maintaining specific logic level combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If logical operations are performed on input signals with overlapping logic level transition periods, then the logical operation speed is improved, but glitches occur in the output signal leading to device malfunction
Solution Approach 1:
The patent applies preliminary action by generating control pulses before the actual logical operation to prepare the circuit in advance. The first control pulse is generated before the first logical operation, and the second control pulse is generated before the second logical operation, ensuring that the circuit is properly synchronized and ready to perform operations without glitches.
Solution Approach 2:
The patent uses control pulses as intermediary signals to mediate between the input signals and the logical operation. The first control pulse mediates the first logical operation by controlling when the first logic circuit operates, and the second control pulse mediates the second logical operation, preventing direct interference between overlapping signal transitions.
2Productivity
If multiple logic circuits operate simultaneously without synchronization, then the processing capacity is improved, but signal interference and malfunctions occur
Solution Approach 1:
The patent implements periodic action by using sequentially generated control pulses to periodically activate different logic circuits. The first control pulse activates the first logic circuit at a specific time, and the second control pulse activates the second logic circuit at a different time, creating a periodic, synchronized operation pattern that maintains signal integrity while utilizing multiple circuits.
3Speed
If input signals are processed without control pulse synchronization, then the operation speed is improved, but logic level transitions overlap causing device malfunction
Solution Approach 1:
The patent uses feedback by generating control pulses based on the timing and state of input signals. The control pulse generation circuit monitors the input signals and generates appropriately timed control pulses that provide feedback control, ensuring that logical operations occur at the correct moments without overlapping transitions, thus maintaining both speed and ease of operation.
Data Source
AI summary
An electronic device may include a pulse delay circuit and a logic circuit. The pulse delay circuit generates an input control pulse based on a command pulse. The logic circuit may be configured to output some input signals from a plurality of input signals as transmitted input signals based on the input control pulse while the input signals maintain a certain logic level combination. The logic circuit may be configured to perform a predetermined logical operation of the transmitted input signals according to a remaining input signal from the plurality of input signals to generate an output signal.