Logic Circuit Switching Factor Adjustment for SEM Violations
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently addressing signal electromigration faults, which can lead to vacancies and deposits within wires or gates due to current flow, necessitating improved simulation and resolution methods.
Innovation Solution
A computer-implemented method for simulating signal electromigration in logic circuits, generating metrics, and automatically resolving violations by adjusting switching factors and reevaluating to confirm resolution, using a signal electromigration limit-to-metric ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated resolution of signal electromigration violations is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The system automatically resolves signal electromigration violations by self-adjusting switching factors without requiring manual intervention. The processor set autonomously evaluates SEM metrics, identifies violations, adjusts switching factors, and reevaluates to confirm resolution, making the system self-sufficient in addressing SEM issues.
Solution Approach 2:
The system changes the switching factor parameter to resolve signal electromigration violations. By dynamically adjusting the switching factor based on evaluated SEM metrics and limit-to-metric ratios, the system modifies circuit behavior to eliminate violations while maintaining functionality.
2Reliability
If signal electromigration simulation is performed, then reliability is improved, but loss of time increases
Solution Approach 1:
The system performs preliminary signal electromigration simulation during the design phase to identify potential violations before fabrication. By evaluating SEM metrics early and resolving violations through automated switching factor adjustment, the system prevents reliability issues from manifesting in the final product, reducing the need for costly post-fabrication corrections.
Solution Approach 2:
The system implements a feedback loop where SEM metrics are evaluated, violations are identified, switching factors are adjusted, and resolution is confirmed through reevaluation. This iterative feedback process ensures reliable resolution of SEM violations while optimizing simulation time by systematically addressing only actual violations.
Data Source
AI summary
An automated signal electromigration violation resolution process is provided for a logic circuit design of an integrated circuit. The automated resolution process includes simulating, by at least one processor set, signal electromigration (SEM) for a logic circuit design of an integrated circuit, where the simulating generates signal electromigration metrics for the logic circuit design. Further, the process includes automatedly resolving, based on evaluating the signal electromigration metrics for violations, a signal electromigration metric violation of the logic circuit design. The automatedly resolving includes generating a signal electromigration limit-to-metric ratio for the metric violation, and auto-adjusting, using the generated limit-to-metric ratio, a switching factor of the logic circuit design to facilitate resolving the signal electromigration violation. Further, the process includes reevaluating the signal electromigration metrics of the logic circuit design using the auto-adjusted switching factor to confirm automated resolution of the signal electromigration metric violation.