Logic Circuit Verification Waveform Comparison
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Solution Overview
Problem
Conventional assertion-based verification methods for logic circuits are limited in verifying logic gate or transistor-level designs, fail to consider timing and analog signal characteristics, and are simulator-specific, leading to lengthy verification processes.
Innovation Solution
A method and apparatus that generate a wave file with waveform data for all nodes of a logic circuit, allowing for verification of functional, timing, and analog characteristics by comparing these waveforms with ideal operations stored in a design reference file, enabling defect detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If assertion-based verification method is used, then logic circuit function can be verified, but verification time becomes excessively long
Solution Approach 1:
The patent creates a reference waveform file that stores ideal waveform data separately from the verification process. This reference file serves as a copy of the expected behavior that can be quickly compared against actual simulation waveforms, eliminating the need for repeated assertion checks during verification.
Solution Approach 2:
The patent performs waveform generation and ideal operation storage in advance before the actual verification process. By pre-computing and storing reference waveforms, the system prepares verification data beforehand, significantly reducing the time required during the actual verification phase.
2Adaptability or versatility
If assertion-based verification method is used, then HDL code-based circuit design can be verified, but logic gate-level or transistor-level circuit design cannot be verified
Solution Approach 1:
The patent develops a universal verification method that works across multiple design levels (HDL code, logic gate-level, and transistor-level). The waveform-based verification approach can handle different circuit representations uniformly, making the verification system multi-functional and applicable to various design stages.
3Reliability
If assertion-based verification method is used, then logic circuit function can be verified, but timing and analog signal characteristics cannot be verified
Solution Approach 1:
The patent merges multiple verification aspects (functional verification, timing verification, and analog signal verification) into a single waveform-based verification framework. By comparing actual waveforms against reference waveforms that encode all these characteristics, the system achieves comprehensive verification without requiring separate complex verification systems for each aspect.
4Adaptability or versatility
If assertion specification macro module is used, then assertion-based verification can be performed, but type of logic simulator is limited
Solution Approach 1:
The patent introduces waveform files as an intermediary format that decouples the verification process from simulator-specific dependencies. By converting simulation results into a standard waveform format for comparison against reference waveforms, the system achieves simulator independence while maintaining verification reliability.
Data Source
AI summary
A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.