Switchable Logic Clusters with Circular Buffers for Runtime Reconfiguration
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Solution Overview
Problem
Existing programmable logic devices, such as FPGAs, can only perform specific logical tasks due to fixed programming, limiting their adaptability to changing functional requirements and preventing dynamic reconfiguration during operation.
Innovation Solution
The implementation of logical elements arranged in clusters with a switching fabric and circular buffers that store configuration instructions, allowing for dynamic reconfiguration of logical elements and interconnections by rotating through different instructions stored in the circular buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable logic devices use fixed programming, then they can perform specific logical tasks reliably, but they lack adaptability to changing functional requirements
Solution Approach 1:
The patent implements dynamic reconfiguration by allowing the logic circuit to transition between different operational states during runtime. The configuration data stored in memory enables the circuit to dynamically alter its logical functionality without physical changes, resolving the contradiction between fixed programming reliability and adaptability to changing requirements.
Solution Approach 2:
The invention changes the operational parameters of the logic circuit by modifying configuration data in memory. By altering the logical state parameters rather than physical structure, the circuit achieves adaptability while maintaining manufacturing simplicity and avoiding increased device complexity.
2Adaptability or versatility
If ASICs are designed with specific programming during production, then manufacturing precision is high, but the circuit cannot be altered after production
Solution Approach 1:
The patent performs preliminary configuration by storing operational data in memory during production, but keeps the circuit adaptable for future reconfiguration. This preliminary setup reduces development time by allowing verification and software testing to occur on reconfigurable hardware before final ASIC production, eliminating the need for separate prototyping stages.
Solution Approach 2:
The invention creates a reconfigurable copy of the intended ASIC functionality using programmable logic elements. This copy can be used for verification and software development, allowing multiple iterations without risking first silicon failure in production ASICs, thus reducing development time while maintaining manufacturing precision for the final product.
3Adaptability or versatility
If programmable logic devices allow dynamic reconfiguration, then adaptability increases, but device complexity increases
Solution Approach 1:
The patent segments the logic circuit into multiple independently reconfigurable logic blocks connected through a switching fabric. Each block can be configured separately, allowing dynamic reconfiguration without requiring the entire circuit to be redesigned. This segmentation reduces the complexity burden by localizing configuration changes rather than managing system-wide complexity.
Solution Approach 2:
The switching fabric acts as an intermediary between logic blocks, managing the complexity of interconnections. By introducing this intermediate layer, the patent enables dynamic reconfiguration of logic blocks without directly complexifying each block's internal structure. The intermediary handles the routing complexity, allowing individual blocks to remain relatively simple while achieving system-level adaptability.
Data Source
AI summary
Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.