Time-Multiplexed Logic Compaction in Emulation Systems

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Solution Overview

Problem

Reprogrammable hardware emulation systems are limited by the number of programmable logic blocks, making it difficult to emulate larger electronic circuit designs efficiently, as they require multiple blocks to replicate repetitive electronic circuits.

Innovation Solution

The system analyzes and emulates multiple repetitive electronic circuits using a single programmable logic element (PLE) within the reprogrammable hardware emulation system, partitioning and mapping circuit instances onto a single PLE to reduce the number of required programmable logic blocks, thereby enabling the emulation of larger designs with fewer blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple programmable logic blocks are used to replicate repetitive electronic circuits, then the emulation capacity increases, but the number of required programmable logic blocks increases

Engineering Contradiction:

Improveemulation capacityVSAvoidnumber of programmable logic blocks

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple repetitive circuit instances into a single programmable logic block by implementing time-multiplexed operation. The system consolidates N identical circuit instances into one PLE, switching between them through time-division multiplexing of input and output ports, thereby reducing the total number of PLEs required from N to 1.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system employs periodic action by sequentially activating different circuit instances at different time intervals within a single PLE. The emulation engine cycles through N different input data sets and corresponding circuit instances in a periodic manner, allowing one PLE to emulate the behavior of N repetitive circuits over time.

Inventive Principle:

Principle #19Periodic action

2Device complexity

If a single programmable logic element is used to emulate multiple repetitive circuits, then the number of required blocks decreases, but the system must process circuits sequentially rather than in parallel

Engineering Contradiction:

Improvenumber of programmable logic blocksVSAvoidemulation speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The system uses periodic action to sequentially process multiple circuit instances at high speed, cycling through N different input data sets in a time-multiplexed fashion. This allows the single PLE to emulate N circuits with effective throughput equivalent to parallel processing, maintaining productivity while reducing hardware complexity.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The system dynamically switches the configuration and input data sets of the PLE in real-time to emulate different circuit instances. The emulation engine dynamically selects which circuit instance to emulate based on the current time slot, enabling flexible and efficient use of the single PLE resource.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11221864B1Combinatorial and sequential logic compaction in electronic circuit design emulation

Publication Date: 2022.01.11 SYNOPSYS INC

AI summary

An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation host system can configure the reprogrammable hardware emulation system to emulate the electronic circuits using the single PLE.