Logic Cone Intersection for Digital Fault Analysis
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Solution Overview
Problem
The increasing complexity of digital electronic device designs with millions of gates has made gate-level timing simulations using Failure Mode and Effects Analysis (FMEA) excessively time-consuming, necessitating a method to reduce simulation time without compromising fault identification.
Innovation Solution
The method involves creating error injection and detection points, generating logic cone lists, determining their intersection, and conducting failure rate analysis to focus simulations on impacted areas, allowing for parallel processing and significant time reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-level timing simulations are performed using FMEA on designs with millions of gates, then comprehensive fault identification is achieved, but simulation time becomes excessively long
Solution Approach 1:
The design is divided into multiple logic cones based on storage elements, allowing the simulation to focus on specific segments rather than the entire design. This segmentation enables the simulation to analyze only the relevant portion of the design affected by errors, significantly reducing simulation time while maintaining comprehensive fault identification capability.
Solution Approach 2:
The simulation applies different analysis depths to different parts of the design. By identifying logic cones and focusing analysis on specific areas where errors may propagate, the simulation allocates computational resources locally to where they are most needed, rather than uniformly across the entire design, thus reducing overall simulation time.
2Reliability
If the entire design is analyzed in each simulation run, then all potential faults are identified, but computational resources are wasted on areas not affected by current errors
Solution Approach 1:
Before conducting the full simulation, the method performs preliminary analysis to identify storage elements and their associated logic cones. This preliminary action prepares the simulation by pre-calculating which areas of the design are relevant to analyze, allowing the main simulation to skip unnecessary portions and focus only on areas where faults may occur or propagate.
Solution Approach 2:
The simulation performs analysis to the extent necessary to identify faults, using logic cone identification to determine the appropriate scope. Rather than always analyzing the entire design, the simulation performs partial analysis limited to relevant logic cones, avoiding excessive computation on areas that do not contribute to fault detection.
Data Source
AI summary
A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.