Combinational Logic Cone Timing Optimization
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Solution Overview
Problem
Current IC design tools face challenges in optimizing timing, leading to inefficiencies in reducing design time and improving quality of results, with existing approaches often relying on heuristic methods that do not guarantee globally optimal solutions.
Innovation Solution
The system determines a logic-function identifier and arrival-time-pattern identifier for a fan-in combinational-logic-cone, allowing for the replacement of the cone with an optimized version based on a database lookup, thereby optimizing IC designs by propagating timing information and minimizing arrival times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If heuristic methods are used for timing optimization, then the optimization process is simpler and faster, but globally optimal solutions are not guaranteed
Solution Approach 1:
The patent pre-computes and stores optimal circuit implementations for all possible Boolean functions and arrival time patterns in a database before actual timing optimization is needed. This preliminary action allows the system to guarantee globally optimal solutions during runtime by simply looking up pre-computed results, rather than performing complex optimizations during the actual design process.
Solution Approach 2:
The patent transforms the continuous space of arrival times into a discrete pattern space by identifying unique arrival time patterns. This dimensionality transformation reduces the infinite continuous parameters to a manageable finite set of patterns, enabling exhaustive enumeration and guaranteeing optimality while keeping the computational process tractable.
2Reliability
If exhaustive enumeration of all Boolean functions and arrival time patterns is performed, then globally optimal solutions are guaranteed, but the computational complexity increases
Solution Approach 1:
The patent performs the computationally intensive exhaustive enumeration of all Boolean functions and arrival time patterns in advance, storing the results in a database. This shifts the computational burden from runtime to preprocessing time, allowing the actual timing optimization to proceed efficiently through simple database lookups while still guaranteeing global optimality.
Solution Approach 2:
The patent creates a comprehensive database that copies and stores all possible optimal circuit implementations for different Boolean functions and arrival time patterns. This pre-computed database serves as a reference library that can be quickly queried during timing optimization without requiring repeated complex computations.
3Measurement precision
If arrival times are treated as unbounded continuous values, then timing accuracy is maximized, but the number of possible cases becomes infinite and unmanageable
Solution Approach 1:
The patent transforms the continuous arrival time values into discrete arrival time patterns by comparing relative timing relationships between signals. This transformation preserves the essential timing information needed for optimization while reducing the infinite continuous space to a finite set of distinguishable patterns that can be enumerated and stored in a database.
Solution Approach 2:
The patent changes the parameter representation from absolute continuous arrival time values to discrete arrival time patterns based on relative timing relationships. This parameter transformation maintains timing accuracy for optimization purposes while making the problem computationally tractable by reducing the number of cases to a manageable finite set.
Data Source
AI summary
Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.