Configurable Logic Data Erasure Verification

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Solution Overview

Problem

Configurable integrated circuits rented by multiple tenants face challenges in ensuring complete data erasure after rental periods, lacking a mechanism for tenants to verify that regions have been properly zeroized by the correct entity before reuse by another tenant.

Innovation Solution

The implementation of a verification system using a digital signature attestation mechanism, where a signing engine generates a digital signature with a private key and a hash value, and a signature verifier engine verifies this signature using a public key to ensure that regions of configurable logic circuits have been correctly erased, providing tenants with assurance of data deletion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If configurable logic regions are reset and reused by different tenants, then resource utilization and cost effectiveness are improved, but tenants cannot verify that their data has been completely erased

Engineering Contradiction:
Improveresource utilizationVSAvoiddata erasure verification
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system implements a feedback mechanism where the security controller generates cryptographic proofs (digital signatures and hash values) that verify data erasure to the tenant. After the provider resets the configurable logic region, the security controller creates an attestation that the region has been properly zeroized, providing verifiable feedback to the tenant about the erasure status.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The verification mechanism is prepared in advance by establishing cryptographic key pairs and security controller configurations before data erasure occurs. The tenant can verify the provider's identity and the erasure authenticity through pre-configured public keys and digital signature verification, ensuring the verification capability exists before the actual erasure takes place.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If cryptographic verification mechanisms are implemented, then data erasure trust is improved, but system complexity increases

Engineering Contradiction:
Improvedata erasure trustVSAvoidverification system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The security controller acts as an intermediary between the provider's reset function and the tenant's verification need. It generates cryptographic proofs (digital signatures, hash values) that bridge the gap between the provider's erasure action and the tenant's trust requirement, simplifying the overall system architecture while maintaining high reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of requiring the tenant to directly verify the physical erasure state, the system creates a cryptographic copy or representation of the erasure proof (digital signature and hash value). This cryptographic copy serves as sufficient evidence of erasure without requiring the tenant to implement complex verification of the actual hardware state.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20240380607A1Systems And Methods For Verification Of Data Erasure
Publication Date: 2024.11.14 ALTERA CORP
  • US20240380607A1 patent drawing
  • US20240380607A1 patent drawing
  • US20240380607A1 patent drawing

AI summary

An integrated circuit includes a region of configurable logic circuits, and a control circuit that generates a digital signature based on a private key and data using a signing engine for verifying that data stored in the region of the configurable logic circuits has been erased. A method is provided for verifying that the region of the configurable logic circuits in the integrated circuit has been erased. The method includes receiving a public key, data, and a digital signature at a control circuit comprising a signature verifier engine, and generating an output that verifies whether the region of the configurable logic circuits has been erased by performing a signature verification of the digital signature using the data and the public key with the signature verifier engine.